Vertical Capacitor Fabrication via Matched-Etch Supporter Patterns

The patent transitions from planar capacitor structures to vertically stacked capacitor structures. By stacking multiple capacitor layers (first capacitor, second capacitor, third capacitor) in the vertical dimension, the total capacitance is increased without increasing the unit cell area, thus resolving the contradiction between miniaturization and capacitance maintenance.

The patent employs composite dielectric materials including high-k dielectric layers (hafnium oxide, hafnium silicon oxide) combined with silicon oxide layers. This composite structure increases the effective capacitance within the reduced area by utilizing materials with higher dielectric constants, allowing capacitance maintenance despite miniaturization.

The patent divides the single dry etching process into multiple sequential etching steps with different conditions. First, a preliminary etching step creates an initial opening, followed by a second etching step that completes the contact hole. Each step uses optimized parameters to prevent void formation and tilt, maintaining both high etching speed and contact hole uniformity.

The patent implements periodic alternation between different etching conditions and intermediate processes (such as removing and reforming mask patterns). This periodic action allows the etching process to correct deviations and prevent tilt phenomena while maintaining overall etching speed through efficient process sequencing.