Vertical Capacitor Integration in Semiconductor Packages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of passive components like capacitors into semiconductor device packages faces challenges due to difficulties in assembly processes and constraints on electrical performance and package footprint dimensions, especially when using standard interconnections and leadframes.
Innovation Solution
A manufacturing process that vertically mounts surface mounting devices (SMDs) on a carrier beside a semiconductor die, using electrically conductive patterns to provide electrical coupling, reducing the package footprint and allowing for both wafer and panel level packaging processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If passive components are embedded in standard leadframe packages using standard interconnection, then the assembly process is simplified, but the electrical performance is constrained and package footprint dimensions are increased
Solution Approach 1:
The patent transitions from planar horizontal mounting of passive components to vertical three-dimensional mounting. Electrical components are positioned vertically above the semiconductor die and connected through conductive patterns on both top and bottom surfaces, utilizing the vertical dimension to reduce footprint while improving electrical performance by eliminating long lateral interconnections
Solution Approach 2:
The patent integrates multiple functions into a compact vertical structure. The semiconductor die, passive components, and interconnection structures are merged into a single three-dimensional package assembly, with conductive patterns serving both as electrical interconnections and as structural elements for component mounting
2Ease of manufacture
If passive components are embedded in standard leadframe packages, then manufacturing is simplified, but layout flexibility is reduced
Solution Approach 1:
By moving to vertical three-dimensional mounting, the patent enables greater layout flexibility. Components can be positioned in the vertical space above the die without consuming additional lateral footprint, allowing more freedom in arranging multiple passive components and optimizing electrical performance without being constrained by planar layout limitations
Solution Approach 2:
The vertical mounting structure serves multiple functions simultaneously: it provides electrical interconnections through conductive patterns, supports passive components in a compact arrangement, and enables flexible layout configurations. This multi-functional approach maintains manufacturing simplicity while significantly improving adaptability
3Area of stationary object
If surface mounting devices are mounted vertically on a carrier beside a die, then package footprint is reduced, but assembly complexity increases
Solution Approach 1:
The vertical mounting approach reduces package footprint by utilizing the vertical dimension instead of lateral space. Multiple passive components are stacked vertically above the semiconductor die, connected through conductive patterns on both top and bottom surfaces, achieving compact integration without proportionally increasing assembly complexity
Solution Approach 2:
The conductive patterns are pre-formed on both the top and bottom surfaces of the semiconductor die before component mounting. This preliminary preparation of electrical interconnection paths simplifies the subsequent assembly process, as components can be directly mounted and connected without requiring complex post-assembly interconnection steps
Data Source
AI summary
An integrated circuit semiconductor dice has first and second opposed surfaces. First and second electrically conductive patterns extending at the first and second opposed surfaces provide electrical coupling to the semiconductor die. An electrical component, such as a capacitor, having a length transverse to the first and second opposed surfaces of the semiconductor die, extends bridge-like between the first and second opposed surfaces. Opposed electrical contact end terminals of the electrical component are coupled to the first and second electrically conductive patterns. The electrical component is thus electrically coupled to the semiconductor die via the first and second electrically conductive patterns at the first and second opposed surfaces.