Vertical Capacitor Structure for PoP Signal Delay Reduction

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving higher integration density and smaller package sizes for electronic components, particularly in Package-on-Package (PoP) technology, where traditional packaging techniques struggle to optimize capacitance and reduce signal delay in compact designs.

Innovation Solution

The implementation of a vertical capacitor structure within an integrated circuit package, utilizing a comb-structure interdigitated design with a dielectric material between opposing plates, embedded within a molding compound, and coupled with redistribution layers and conductive connectors to enhance capacitance and reduce signal delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional packaging techniques are used in PoP technology, then manufacturing simplicity is maintained, but integration density and capacitance optimization are insufficient

Engineering Contradiction:

Improveintegration densityVSAvoidpackage structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent transitions from traditional planar capacitor layouts to a vertical three-dimensional structure. The capacitor plates are arranged vertically with one plate on the anode bump and another plate on the cathode bump, utilizing the vertical dimension to achieve higher integration density without increasing lateral footprint. This dimensional change allows capacitance optimization in compact PoP packages.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitor structure is nested within the existing package architecture. The anode plate is formed on the anode bump surface, the dielectric layer is deposited over it, and the cathode plate is formed on the cathode bump, effectively nesting the capacitor within the bond pad and bump structures already present in PoP technology.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Area of stationary object

If package size is reduced for smaller components, then area utilization is improved, but capacitance and signal delay performance deteriorate

Engineering Contradiction:

Improvepackage areaVSAvoidsignal delay and capacitance

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

By arranging capacitor plates vertically rather than laterally, the design achieves high capacitance values without requiring large lateral area. The vertical separation between anode and cathode plates allows sufficient capacitance to be achieved within the compact footprint of smaller packages, maintaining signal delay performance while reducing overall package area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Productivity

If operational frequency is increased for denser integration, then productivity is improved, but signal delay and RC values become problematic

Engineering Contradiction:

Improveoperational frequencyVSAvoidsignal delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The vertical capacitor structure changes the geometric parameters of the capacitor, specifically the distance between plates and the effective area. By optimizing these parameters in the vertical configuration, the RC time constant is reduced, enabling higher operational frequencies with acceptable signal delay characteristics for dense integration applications.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for increased operational frequency and denser integration by providing a favorable RC value and allocating design area efficiently, enabling smaller and more integrated electronic components.

Implementation Method 1

The capacitor comprises a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

utilizing a comb-structure interdigitated design with a dielectric material between opposing plates

Methodology Applied

Scientific EffectDielectric: Dielectric

Data Source

PatentUS8653626B2Package structures including a capacitor and methods of forming the same

Publication Date: 2014.02.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side.