Vertically-elongated Capacitors with Scaffold Structures
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Solution Overview
Problem
Current memory device architectures, including DRAM and FeRAM, face challenges in optimizing capacitor design and fabrication methods, particularly in creating vertically-elongated capacitors with efficient storage nodes supported by vertically-stacked scaffold structures.
Innovation Solution
The method involves forming vertically-elongated capacitors with storage nodes supported by vertically-stacked scaffold structures, where semiconductor pillars with doped source/drain regions are used, and digit lines and wordlines are integrated with dielectric material, enabling precise voltage control for current flow and addressing individual memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional capacitor designs are used in DRAM and FeRAM, then fabrication processes are simpler, but memory cell efficiency and addressability are reduced
Solution Approach 1:
The patent transitions from planar capacitor structures to vertically-elongated three-dimensional capacitor structures. The capacitors extend substantially vertically from bit lines, utilizing the vertical dimension to increase storage capacity and improve memory cell efficiency while maintaining a compact footprint on the substrate.
Solution Approach 2:
The capacitor structure is segmented into distinct functional regions including vertically-stacked scaffold structures, storage nodes, and dielectric material regions. This segmentation allows for optimized performance of each component while enabling precise voltage control for addressing individual memory cells.
2Manufacturing precision
If vertically-elongated capacitors with vertically-stacked scaffold structures are implemented, then memory cell addressability and current control are improved, but fabrication complexity increases
Solution Approach 1:
The fabrication process employs preliminary patterning steps where placeholder structures are formed first, followed by selective removal and replacement with the final vertically-elongated capacitor structures. This preliminary action enables precise positioning and alignment of the complex three-dimensional capacitor geometry.
Solution Approach 2:
The patent uses intermediate scaffold structures as placeholders during fabrication that guide the formation of the final capacitor geometry. These scaffold structures serve as intermediaries that simplify the manufacturing process by providing a template for the complex vertically-stacked architecture, which is then refined to achieve the final precise structure.
3Reliability
If vertically-stacked scaffold structures are used to support storage nodes, then capacitor stability and performance are enhanced, but device complexity increases
Solution Approach 1:
The capacitor structure employs composite materials including dielectric material, conductive storage nodes, and vertically-stacked scaffold structures. This composite architecture combines materials with complementary properties to enhance capacitor stability, provide mechanical support, and optimize electrical performance while managing the inherent structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency and addressability of memory cells by allowing for selective control of current flow through the use of vertically-stacked scaffold structures, improving the overall performance and fabrication of both DRAM and FeRAM memory devices.
Implementation Method 1
semiconductor pillars with doped source/drain regions are used, and digit lines and wordlines are integrated with dielectric material, enabling precise voltage control for current flow
Data Source
AI summary
Some embodiments include an integrated assembly having bottom electrodes coupled with electrical nodes. Each of the bottom electrodes has a first leg electrically coupled with an associated one of the electrical nodes, and has a second leg joining to the first leg. First gaps are between some of the bottom electrodes, and second gaps are between others of the bottom electrodes. The first gaps alternate with the second gaps. Insulative material and conductive-plate-material are within the first gaps. Scaffold structures are within the second gaps and not within the first gaps. Capacitors include the bottom electrodes, regions of the insulative material and regions of the conductive-plate-material. The capacitors may be ferroelectric capacitors or non-ferroelectric capacitors. Some embodiments include methods of forming integrated assemblies.