Vertical Capacitor Stacking Reduces Column Height in CMOS Imager
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Solution Overview
Problem
The layout size of capacitors in column sample-and-hold circuitry in CMOS imagers is large, which hinders further miniaturization and increases the column height, making it difficult to achieve further profitability and compact device design.
Innovation Solution
The capacitors are arranged in a vertical stack over the columns they service, allowing for a reduced overall column height by integrating intercolumn spacings, while maintaining the same capacitance values and preserving the pixel array and sensing circuitry design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If capacitors are arranged in traditional lateral layout, then capacitance value is maintained, but column height increases and layout size becomes large
Solution Approach 1:
The patent transitions from a two-dimensional lateral arrangement of capacitors to a three-dimensional vertical stacking configuration. Multiple capacitor pairs are stacked vertically over the columns they service, utilizing the vertical dimension to reduce the lateral layout footprint while maintaining the required capacitance values and electrical performance.
2Area of stationary object
If capacitor size is reduced for miniaturization, then layout space decreases, but capacitance value and sensing performance deteriorate
Solution Approach 1:
By stacking capacitors vertically, the patent achieves miniaturization in the lateral plane without reducing individual capacitor dimensions. The vertical stacking allows multiple capacitor pairs to share the same lateral footprint, reducing overall layout space while each capacitor maintains its required capacitance value for proper sensing performance.
Solution Approach 2:
The patent merges multiple capacitor pairs vertically into a compact stack, allowing them to share common column connections and control circuitry. This consolidation reduces the overall layout space while maintaining the functional independence and performance of each capacitor pair.
3Length of stationary object
If vertical stacking is implemented, then column height is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the capacitor structure into multiple vertically-stacked pairs, each pair serving specific columns. This segmentation allows for modular fabrication and assembly, where each stacked pair can be manufactured and connected systematically, reducing overall manufacturing complexity despite the three-dimensional configuration.
Data Source
AI summary
Improved column sample-and-hold (CSH) circuitry particularly useful in a CMOS imager is disclosed. In the improved circuitry layout, the overall column height of the CSH circuitry is reduced by providing a plurality of pairs of sampling and reference capacitors in a vertical stack over the columns that the capacitors service. The number of pairs provided in the vertical stack is subject to optimization, and for a given set of design constraints, a certain form factors can prove to be optimal. No modification needs to be made to the pixel array (such as pixel pitch), and the sensing circuitry otherwise requires no electrical or process modifications as the values for the capacitances as well as other design constraint are preserved. However, the vertical stacking of the plurality of pairs of capacitors reduces the overall column height (CH), which conserves layout space on the CMOS imager integrated circuit.