Vertical Capacitor Stacking for CMOS Imager Column Height Reduction
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Solution Overview
Problem
The significant layout size of capacitors in column sample-and-hold circuitry in CMOS imagers hinders further miniaturization and increases the column height, making it difficult to achieve further profitability and compact device design.
Innovation Solution
The capacitors are vertically stacked over columns, allowing for a reduced overall column height by integrating intercolumn spacings, while maintaining the same capacitance values and preserving the pixel array and sensing circuitry, thus optimizing the form factor to minimize layout space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If capacitors are arranged horizontally in traditional layout, then ease of manufacture is maintained, but column height increases and layout size becomes large
Solution Approach 1:
The patent transitions from horizontal arrangement to vertical stacking of capacitors, utilizing the vertical dimension to reduce column height. Multiple capacitors are stacked one above another in the vertical direction rather than placing them side-by-side horizontally, thereby compressing the column height while maintaining manufacturing feasibility through standard vertical stacking processes.
Solution Approach 2:
The patent merges multiple capacitor structures into a compact vertical stack, combining what would traditionally be separate horizontal elements into a single vertical column. This merging approach integrates the capacitors more densely, reducing the overall column height and layout footprint while maintaining electrical functionality.
2Quantity of substance
If capacitor size is increased to maintain capacitance values, then sensing functionality is preserved, but layout area increases and miniaturization is hindered
Solution Approach 1:
The patent exploits the vertical dimension to accommodate larger effective capacitance values without increasing horizontal layout area. By stacking capacitors vertically, the design achieves the required capacitance quantities through increased vertical integration rather than horizontal expansion, thereby maintaining compact layout area while preserving sensing functionality.
Solution Approach 2:
The patent implements a nested arrangement where capacitor structures are stacked one within another in the vertical dimension, similar to nested dolls. This nesting approach allows multiple capacitor elements to occupy a compact horizontal footprint while accumulating the necessary total capacitance value through vertical stacking, thus resolving the contradiction between capacitance quantity and layout area.
3Productivity
If traditional horizontal capacitor arrangement is used, then manufacturing process is simple, but device miniaturization and profitability are limited
Solution Approach 1:
The patent employs vertical stacking to achieve device miniaturization by utilizing the third dimension (vertical axis) rather than being constrained to two-dimensional horizontal layout. This dimensional transition enables smaller column heights and more compact imager devices, enhancing miniaturization capability and potential profitability despite increased layout design complexity.
Solution Approach 2:
The patent introduces flexibility in the capacitor arrangement by allowing dynamic optimization of vertical stacking configurations. Rather than being locked into a fixed horizontal pattern, the design can dynamically adjust vertical stack heights and capacitor distributions to achieve optimal miniaturization for different device requirements, thereby improving adaptability and productivity.
Data Source
AI summary
Improved column sample-and-hold (CSH) circuitry particularly useful in a CMOS imager is disclosed. In the improved circuitry layout, the overall column height of the CSH circuitry is reduced by providing a plurality of pairs of sampling and reference capacitors in a vertical stack over the columns that the capacitors service. The number of pairs provided in the vertical stack is subject to optimization, and for a given set of design constraints, a certain form factors can prove to be optimal. No modification needs to be made to the pixel array (such as pixel pitch), and the sensing circuitry otherwise requires no electrical or process modifications as the values for the capacitances as well as other design constraint are preserved. However, the vertical stacking of the plurality of pairs of capacitors reduces the overall column height (CH), which conserves layout space on the CMOS imager integrated circuit.