Vertical Capacitor Structure for Non-Volatile Memory Charge Pump
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Solution Overview
Problem
There is a need for increased capacitance per unit area in memory devices, particularly in 3D non-volatile memory devices with vertically stacked word lines, where the capacity of charge pumps in peripheral circuits must be enhanced to support higher integration densities.
Innovation Solution
A vertical capacitor structure is introduced, featuring a substrate with active patterns and a gate pattern above the channel region, along with capacitor electrodes extending vertically, allowing for different voltages to be applied to each electrode to form both channel and vertical capacitors, thereby increasing capacitance without turning on current in the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of word lines stacked on the substrate increases to achieve higher integration density, then the memory capacity increases, but the capacity of the charge pump in the peripheral circuit must be increased, requiring more area
Solution Approach 1:
The patent transitions from a planar capacitor structure to a vertical capacitor structure by extending capacitor electrodes in the vertical direction above the substrate. This dimensional change allows the charge pump to achieve higher capacitance without increasing the horizontal area occupied on the substrate, thus resolving the contradiction between memory capacity scaling and charge pump area requirements
Solution Approach 2:
The capacitor electrodes are positioned vertically above the substrate and nested within the peripheral circuit area, utilizing the vertical space above existing structures. This nesting approach allows the charge pump components to be stacked vertically rather than spread horizontally, reducing the area footprint while maintaining or increasing capacitance capacity
2Quantity of substance
If a conventional planar capacitor structure is used, then the device layout is simple, but the capacitance per unit area is limited
Solution Approach 1:
The patent introduces vertical capacitor electrodes extending above the substrate, transforming the capacitor structure from a two-dimensional planar configuration to a three-dimensional vertical configuration. This enables significantly higher capacitance per unit area by utilizing the vertical dimension, while the underlying substrate and connection structures remain relatively simple
Solution Approach 2:
The capacitor structure is segmented into multiple vertical electrodes positioned at different heights and locations above the substrate. This segmentation allows for increased total capacitance by creating multiple capacitor elements in series and parallel configurations within the vertical space, thereby increasing capacitance per unit area without requiring a completely complex monolithic structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the integration degree of capacitors, increases capacitance per unit area, and improves space efficiency by allowing a larger capacity charge pump within a reduced area, ultimately reducing the chip size of non-volatile memory devices.
Implementation Method 1
a first capacitor electrode in contact with the first gate pattern, to which a first voltage is applied, and forming a channel capacitor with the channel region
Implementation Method 2
a second capacitor electrode in contact with the first active pattern and to which a second voltage is applied, the second voltage being different from the first voltage, and a third capacitor electrode in contact with the second active pattern and to which the second voltage is applied
Data Source
AI summary
A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.