Vertical Capacitor Symmetry via Support Layer
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Solution Overview
Problem
Current methods for manufacturing semiconductor devices face challenges in increasing electrostatic capacity while maintaining a high degree of integration, particularly in forming vertical capacitors that are prone to asymmetry, bending, or collapsing due to height increases, which affects their reliability.
Innovation Solution
A method involving the sequential stacking of molding and support layers, forming openings, and filling them with a sacrificial layer having etching characteristics similar to the support and molding layers, allows for the creation of symmetrical vertical holes and electrodes, thereby preventing capacitor asymmetry and ensuring structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of capacitor is increased to increase electrostatic capacity, then electrostatic capacity is improved, but vertical capacitor becomes prone to asymmetry, bending, or collapsing
Solution Approach 1:
A support layer is formed in advance before forming the vertical capacitor to provide structural support during the capacitor formation process. The support layer is positioned at a specific depth from the upper surface of the substrate, creating a framework that prevents asymmetry, bending, or collapsing of the vertical capacitor as it is built upward to increase height and electrostatic capacity.
Solution Approach 2:
The support layer acts as an intermediary structural element between the substrate and the vertical capacitor. This intermediate layer provides mechanical support and stability to the vertical capacitor during and after formation, enabling the capacitor to achieve greater height for increased electrostatic capacity without suffering from structural defects such as asymmetry, bending, or collapsing.
2Ease of manufacture
If sacrificial layer has different etching rate from support layer, then sacrificial layer can be selectively removed, but vertical hole becomes asymmetrical causing capacitor asymmetry
Solution Approach 1:
The etching rate parameter of the sacrificial layer is adjusted to be substantially the same as that of the support layer. This parameter matching ensures that when both layers are etched to form vertical holes, they are removed at the same rate, resulting in symmetrical vertical holes. The sacrificial layer can still be selectively removed after the vertical capacitor is formed, as it is positioned within the vertical hole and can be accessed through the etched opening.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of vertical capacitors by maintaining symmetry and preventing structural issues, allowing for increased electrostatic capacity without compromising the degree of integration.
Implementation Method 1
forming a plurality of vertical holes passing through the support layer and the molding layer, forming a lower electrode within the plurality of vertical holes; and removing the sacrificial layer and the molding layer
Implementation Method 2
forming a plurality of vertical holes through the support layer and through the molding layer by dry etching the support layer and the molding layer
Data Source
AI summary
A method of manufacturing a semiconductor device includes stacking a molding layer and a preliminary support layer on a substrate, forming a support layer having a plurality of openings by removing at least a portion of the preliminary support layer, forming a sacrificial layer by filling the plurality of openings with a different material from a material of the molding layer and from a material of the preliminary support layer, forming a plurality of vertical holes through the support layer and through the molding layer, forming a lower electrode within the plurality of vertical holes, and removing the sacrificial layer and the molding layer.