Vertical Capacitors on STI Regions for Charge Pump Parasitic Reduction

The patent transitions from planar (2D) capacitor structures to vertical (3D) capacitor structures by stacking conductive plates and dielectric layers vertically on the STI region. This dimensional change eliminates parasitic capacitance interference from the substrate while maintaining the necessary capacitance function, and the vertical structure can be formed using standard deposition and etching processes without requiring additional photomask steps.

The patent extracts the capacitor structure from the active transistor region and places it on the shallow trench isolation (STI) region. By locating the vertical capacitor on the STI region rather than on active device areas, the design removes parasitic capacitance coupling between the capacitor and surrounding circuit elements, thereby improving charge pump circuit performance without adding manufacturing complexity.

The patent merges the formation of vertical capacitor structures with the existing flash memory fabrication process sequence. The alternating deposition of conductive layers (e.g., polysilicon, metal) and dielectric layers (e.g., oxide, nitride) is integrated into the standard process flow, where the same deposition and patterning steps that form transistor gates and interconnects are also used to build the vertical capacitor stacks on the STI region, eliminating the need for separate dedicated capacitor fabrication processes.

The vertical capacitor structure serves multiple functions: it provides the necessary capacitance for charge pump operation, acts as an isolated structure on the STI region to avoid parasitic effects, and utilizes the same material layers and deposition processes as the surrounding flash memory devices. This multi-functionality approach allows a single fabrication process to simultaneously create both the memory cells and the charge pump capacitors without requiring specialized manufacturing steps.