Vertical Cavity LED Structure for Efficiency Droop

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Solution Overview

Problem

High-brightness and high-power LEDs face efficiency droop issues due to reduced quantum efficiency at high current densities, limiting their performance and manufacturing costs, despite advancements in internal and external quantum efficiencies.

Innovation Solution

A semiconductor device manufacturing method involving a substrate with a one- or two-dimensional repetitive pattern, formed in the substrate or epitaxial layer, which increases the surface area and reduces carrier density, allowing for high current and high breakdown voltage operations while maintaining high internal quantum efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If high current density is applied to achieve high power output, then power increases, but quantum efficiency decreases due to efficiency droop

Engineering Contradiction:
Improvepower outputVSAvoidquantum efficiency
Core Design Contradiction:
PowerVSLoss of energy

Solution Approach 1:

The patent transitions from a planar two-dimensional active region to a three-dimensional vertical cavity structure. The light emitting cavity extends vertically through multiple quantum wells stacked along the growth direction, enabling high power output while maintaining low carrier density through the vertical dimension. This dimensional change allows current to be injected through a small aperture area while the emission volume extends vertically, achieving high power without efficiency droop.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the operational parameters by confining carriers in a vertical cavity with specific depth and width dimensions. The cavity depth (extending through multiple quantum wells) and aperture area are optimized to maintain low carrier density at high current injection levels. This parameter change enables operation at high current densities without the typical efficiency droop observed in planar structures.

Inventive Principle:
Principle #35Parameter changes

2Illumination intensity

If current density is increased to improve brightness, then light output increases, but internal quantum efficiency decreases

Engineering Contradiction:
Improvelight outputVSAvoidinternal quantum efficiency
Core Design Contradiction:
Illumination intensityVSLoss of energy

Solution Approach 1:

The vertical cavity structure utilizes the third dimension (growth direction) to separate the current injection area (small aperture) from the emission volume (extended vertically). This allows high current injection to produce high light output while the vertical distribution of quantum wells maintains low carrier density, preserving internal quantum efficiency even at high brightness levels.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If planar structure is used for simplicity, then device complexity is low, but surface area is limited restricting power output

Engineering Contradiction:
Improvestructure simplicityVSAvoidactive surface area
Core Design Contradiction:
Device complexityVSArea of moving object

Solution Approach 1:

The patent resolves this contradiction by extending the active region vertically rather than expanding laterally. The vertical cavity structure provides large effective emission area through the stacked quantum wells along the growth direction while maintaining a compact planar footprint. This approach achieves high power output capability without the complexity of lateral expansion or multiple planar layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method achieves significantly increased internal quantum efficiency, maintaining high efficiency at high current densities and enabling high-power applications with low carrier density and high breakdown voltage, thus overcoming efficiency droop challenges.

Implementation Method 1

forming a one- or two-dimensional repetitive pattern, each part of the pattern having an aspect ratio in the range of about 0.1 to 50... which increases the surface area and reduces carrier density

Methodology Applied
Scientific EffectSurface area expansion through repetitive patterning:

Implementation Method 2

Semiconductor device and method... specially adapted for light emission... electroluminescent light sources

Methodology Applied
Scientific EffectElectroluminescence: Electroluminescence

Data Source

PatentUS9196477B2Semiconductor device and method
Publication Date: 2015.11.24 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • US9196477B2 patent drawing
  • US9196477B2 patent drawing
  • US9196477B2 patent drawing

AI summary

A semiconductor device and a method of manufacturing the device is disclosed. In one aspect, a method includes providing a substrate, providing a first epitaxial semiconducting layer on top of the substrate, and forming a one- or two-dimensional repetitive pattern, each part of the pattern having an aspect ratio in the range of about 0.1 to 50.