Vertical Cell Single-Crystalline Channel via Metal-Induced Crystallization
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in reducing device size and improving performance, particularly in forming vertically stacked memory cells with efficient carrier mobility and low leakage current.
Innovation Solution
The method involves forming a vertical cell structure with a single-crystalline channel area by alternating interlayer insulating and sacrificial layers, forming a channel hole, and using metal-induced crystallization to convert amorphous silicon into single-crystalline silicon, followed by the formation of bit lines and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertically stacked memory cells are formed to reduce device size, then device density is improved, but carrier mobility and leakage current performance deteriorate
Solution Approach 1:
The patent transitions from planar memory cell structures to vertically stacked three-dimensional structures, allowing multiple memory cells to be stacked along the vertical dimension. This enables increased device density while maintaining individual cell performance through the use of single-crystalline channel structures that preserve carrier mobility even in the vertical configuration.
Solution Approach 2:
The patent employs metal-induced crystallization (MIC) to transform amorphous silicon into single-crystalline silicon, fundamentally changing the material phase and crystal structure. This parameter change in the channel material's crystallinity directly improves carrier mobility and reduces leakage current, resolving the performance deterioration that typically occurs in vertically stacked devices.
2Ease of manufacture
If amorphous silicon is used in vertical channel structures, then manufacturing is simplified, but carrier mobility and speed performance deteriorate
Solution Approach 1:
The patent utilizes metal-induced crystallization to induce a phase transition from amorphous silicon to single-crystalline silicon in the channel region. The amorphous silicon is first deposited using simple PECVD methods, then metal nanoparticles are introduced and heated to trigger in-situ crystallization, achieving high-performance single-crystalline structures without complex epitaxial growth processes.
Solution Approach 2:
The patent replaces traditional mechanical or chemical epitaxial growth methods with a thermal-field-based metal-induced crystallization process. Instead of using complex vapor-phase epitaxy equipment, the invention uses heated processing chambers with metal-containing atmospheres to induce crystallization, simplifying the manufacturing system while achieving superior crystal quality.
3Speed
If single-crystalline channel structures are formed in vertical cells, then carrier mobility and speed are improved, but device complexity increases
Solution Approach 1:
The patent incorporates metal nanoparticles into the amorphous silicon layer during the deposition process or as a preliminary step before crystallization. This preliminary introduction of metal catalysts prepares the structure for subsequent low-temperature crystallization, enabling single-crystalline formation without requiring high-temperature epitaxial equipment or complex multi-step processes.
Solution Approach 2:
The patent uses metal nanoparticles as intermediary agents to facilitate the crystallization of silicon. These metal particles act as catalysts that lower the crystallization temperature and enable single-crystalline formation from amorphous silicon through a simplified thermal process, avoiding the need for complex epitaxial growth systems while achieving high carrier mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with superior carrier mobility, high speed operation, low leakage current, and extended data retention, enabling stable performance under lower voltage and current conditions.
Implementation Method 1
Annealing is performed to change the amorphous silicon layer and the amorphous channel active pattern into a single-crystalline silicon layer and a single-crystalline channel active pattern, respectively
Data Source
AI summary
Methods of fabricating a vertical cell semiconductor device including forming a hole passing through a stacked structure of alternating insulating and sacrificial layers on a substrate, forming an amorphous silicon layer conforming to an inner wall of the hole, forming a silicon region on the amorphous silicon layer, and metal induced crystallizing the amorphous silicon layer via the silicon region to form a single-crystalline channel structure in the hole.