Vertical CFET Channel Structure With Buffer Layer for Shared Electrodes
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Solution Overview
Problem
The development of Complementary Full-surrounding gate cylindrical nanowire or nanosheet field Effect Transistors (CFET) is limited by the complexity and difficulty in controlling the shared source or drain electrode connecting line process, leading to increased area occupation and reduced gate control capability due to the use of horizontally arranged GAA transistors.
Innovation Solution
A semiconductor structure with a conductive channel structure comprising sequentially stacked first and second conductive channel layers, doped regions, and a conductive buffer layer to reduce electrical interference, along with a gate structure arranged around the channels, which allows for vertical arrangement of conductive channels to minimize horizontal area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If CFET devices share source/drain electrodes vertically, then chip area is reduced and integration is improved, but process complexity increases and control difficulty increases
Solution Approach 1:
The patent transitions from horizontal arrangement to vertical stacking of nFET and pFET channels, moving the device architecture into the third dimension. This vertical configuration reduces the horizontal chip area while enabling shared source/drain electrodes between nFET and pFET, thereby improving integration density despite increased process complexity
Solution Approach 2:
The patent merges the source/drain electrode structures of nFET and pFET into shared common electrodes. By combining these previously separate components into unified shared structures, the chip area is reduced and device integration is improved, although this merging increases the complexity of process control
2Ease of manufacture
If horizontally arranged GAA transistors are used, then source/drain connection is simplified, but area occupation increases and gate control capability decreases
Solution Approach 1:
The patent replaces horizontal arrangement with vertical stacking of multiple channels, transitioning the architecture to three-dimensional space. This vertical configuration significantly reduces horizontal area occupation while maintaining manufacturability through systematic process design
3Reliability
If ultra-steep PN junction doping is used, then source-drain punch-through is prevented, but thermal budget is limited and manufacturing precision becomes difficult
Solution Approach 1:
The patent implements selective doping with different concentration profiles in different spatial locations. By applying local quality variations through selective area doping and adjusting doping concentrations at specific regions, the design achieves punch-through prevention while managing the challenges of ultra-steep junction manufacturing precision
Solution Approach 2:
The patent employs doping concentration gradients with ultra-steep profiles to prevent source-drain punch-through. By changing the doping parameters to create sharp concentration transitions, the design achieves reliable punch-through prevention, though this creates challenges for manufacturing precision and thermal budget management
Data Source
AI summary
A semiconductor structure includes a base and a conductive channel structure, in which the conductive channel structure includes a base and a conductive channel structure which includes a first conductive channel layer including a first conductive channel, and a first and a second doped regions respectively located at two ends of the first conductive channel, a second conductive channel layer including a second conductive channel, and a third and a fourth doped regions respectively located at two ends of the second conductive channel and a conductive buffer layer configured to reduce electrical interference between the first and the third doped regions; a first conductive layer in contact with the second doped region; a second conductive layer nested on the conductive channel structure and in contact with the first and the third doped regions; and a gate structure arranged around the first conductive channel and the second conductive channel.