Vertical C-FET Structure With Strain-Tuned SRAM Current Ratio
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Solution Overview
Problem
Existing complementary field effect transistor (C-FET) structures and fabrication processes are inadequate in providing optimal performance, particularly in SRAM applications where the on-state current of p-type devices is not sufficiently smaller than that of n-type devices.
Innovation Solution
The method involves forming a semiconductor device with a vertical C-FET structure by selectively depositing a dielectric layer to modify strain on the channel, blocking epitaxial formation of source/drain features, and trimming the channel width of bottom transistors to achieve different performance attributes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing C-FET structures and fabrication processes are used, then manufacturing simplicity is maintained, but device performance is insufficient for optimal SRAM applications
Solution Approach 1:
The patent applies local quality by selectively modifying specific regions of the C-FET structure. Different strain conditions are applied to n-type and p-type transistors through selective dielectric layer deposition and targeted epitaxial growth blocking. The channel width of bottom transistors is trimmed differently from top transistors, creating locally optimized performance characteristics for SRAM applications where p-type devices need approximately half the on-state current of n-type devices.
Solution Approach 2:
The patent changes multiple physical parameters to optimize device performance. Strain parameters are modified through selective dielectric layer deposition that alters mechanical stress on channel regions. Epitaxial formation is blocked in specific regions to control source/drain feature development. Channel width parameters are adjusted through selective trimming processes, creating performance differentiation between n-type and p-type transistors without requiring complete redesign of the fabrication process.
2Reliability
If the on-state current of p-type devices is reduced to half that of n-type devices, then SRAM cell performance is optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by pre-establishing structural differences between n-type and p-type transistors before final device formation. Selective dielectric layer deposition is performed early in the process to pre-condition strain environments. Epitaxial formation blocking is implemented in advance to control source/drain development. These preliminary modifications to the bottom transistor channel width and strain conditions create a foundation that naturally leads to the desired current ratio, reducing the need for precise final-stage adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of transistors with varied performance attributes, optimizing the on-state current of p-type devices to be about half that of n-type devices, thereby improving SRAM cell performance.
Implementation Method 1
selectively depositing a dielectric layer to modify strain on the channel
Implementation Method 2
blocking epitaxial formation of source/drain features
Data Source
AI summary
Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a substrate, a first semiconductor layer over the substrate, a second semiconductor layer over the first semiconductor layer and including a channel region sandwiched between a first source/drain region and a second source/drain region, a first plurality of nanostructures disposed over the channel region, a first leakage block layer over the first source/drain region, a second leakage block layer over the second source/drain region, a dielectric layer on the first leakage block layer, a first source/drain feature on the dielectric layer and in contact with first sidewalls of the first plurality of nanostructures, and a second source/drain feature disposed on the second leakage block layer and in contact with second sidewalls of the first plurality of nanostructures. The first leakage block layer and the second leakage block layer includes an undoped semiconductor material.