Vertical-Channel 1T0C Memory Structure for Higher DRAM Density
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Solution Overview
Problem
The existing Dynamic Random Access Memory (DRAM) technology faces challenges in reducing the size of storage units due to leakage currents and the need for capacitor structures, which limits the storage performance and integration density.
Innovation Solution
The proposed solution involves a memory structure with transistors and storage layers where conductive channels extend perpendicular to the substrate, allowing for electric charge storage and transfer without capacitors, resulting in a 1T0C structure that reduces the size and increases integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitor structures are used for charge storage in DRAM, then storage function is achieved, but storage unit size increases and integration density decreases
Solution Approach 1:
The patent extracts and removes the capacitor component from the traditional 1T1C DRAM structure, creating a capacitorless 1T0C memory cell. The storage function is achieved through charge trapping in the transistor's conductive channel using trap states in the oxide layer, eliminating the need for separate capacitor structures and thereby reducing storage unit size and increasing integration density.
Solution Approach 2:
The transistor structure in the patent performs multiple functions: it acts as both the access device and the storage element. The conductive channel with trap states in the oxide layer serves dual purposes of charge transport and charge storage, replacing the separate capacitor component and simplifying the overall memory cell structure.
2Ease of manufacture
If traditional 1T1C structure is used, then storage function is reliable, but manufacturing complexity increases
Solution Approach 1:
The patent merges the storage function into the transistor structure by creating trap states within the oxide layer of the conductive channel. This combination of access device and storage element into a single integrated structure simplifies the manufacturing process by eliminating the need for separate capacitor fabrication, alignment, and integration steps required in traditional 1T1C DRAM.
3Quantity of substance
If storage layers are added to each transistor, then charge storage capacity increases, but device structure becomes more complex
Solution Approach 1:
The patent embeds the storage function within the existing transistor structure by creating trap states in the oxide layer that forms part of the conductive channel. The storage layers are nested within the transistor's own structure rather than being added as external components, thereby increasing charge storage capacity without significantly increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the size of memory units, enhances storage efficiency, and simplifies the manufacturing process by eliminating the need for capacitors, thereby improving the integration density and performance of DRAM technology.
Implementation Method 1
The storage layers are configured to store electric charges and transfer the electric charges between the storage layers and the conductive channels interconnected therewith
Data Source
AI summary
A memory and a method for manufacturing the same are provided. The memory includes a substrate; at least one pair of transistors on a surface of the substrate, in which conductive channels of the transistors extend in a direction perpendicular to the surface of the substrate; storage layers, which each are located at one side of the transistors and are interconnected with the conductive channels of the transistors, the pair of transistors is located between two storage layers corresponding to the pair of transistors, and the storage layers are configured to store electric charges and transfer the electric charges between the storage layers and the conductive channels interconnected therewith.