Vertical Channel Memory Cell Layout With Air-Gap Word Line Isolation
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing integration density and improving electrical characteristics and production yield as they are scaled down, particularly in maintaining effective resistance and current driving characteristics.
Innovation Solution
The semiconductor device incorporates a design with vertical channel transistors, including a first and second bit line, active pillars, gate insulating patterns, word lines, and a protection pattern with an air gap between the word lines to reduce electric interference and enhance integration density and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are scaled down to increase integration density, then integration density is improved, but electrical characteristics and production yield deteriorate
Solution Approach 1:
The patent transitions from planar transistors to vertical channel transistors, utilizing the vertical dimension to increase integration density while maintaining electrical performance. The vertical channel structure allows higher density packing without degrading the electrical characteristics that would normally occur with planar scaling.
Solution Approach 2:
The patent introduces a protection pattern as an intermediary structure between adjacent word lines. This protection pattern prevents direct electrical interference between word lines, thereby maintaining reliable electrical characteristics in the high-density vertical channel configuration.
2Reliability
If protection pattern is added between word lines to reduce electric interference, then electrical characteristics are improved, but device complexity increases
Solution Approach 1:
The protection pattern is formed by controlling the etch depth parameter to create air gaps at specific locations between word lines. By adjusting etch parameters rather than adding entirely new structural elements, the patent reduces electrical interference while minimizing increases in device complexity.
Solution Approach 2:
The patent removes material to create air gaps between word lines through the protection pattern. This extraction of material creates natural electrical isolation without requiring additional insulating layers or complex structural additions, thereby improving electrical characteristics with minimal complexity increase.
3Reliability
If air gap is introduced between word lines to reduce electric interference, then electrical characteristics are improved, but manufacturing precision requirements increase
Solution Approach 1:
The protection pattern structure is designed to self-form air gaps through the etching process itself. The air gaps emerge naturally from the protective structure's geometry and the etch process, eliminating the need for separate air gap formation steps and reducing manufacturing precision requirements compared to methods requiring precise direct air gap creation.
Data Source
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AI summary
A semiconductor device may include a first bit line that extends in a first direction, a first active pillar and a second active pillar on the first bit line, a first gate insulating pattern enclosing the first active pillar, a second gate insulating pattern on the second active pillar, a first word line and a second word line that extends in a second direction that intersects the first direction, and a protection pattern between the first and second word lines. An air gap is between the first and second word lines and may be adjacent to the protection pattern.