Vertical Channel Semiconductor Device with Air Gaps
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Solution Overview
Problem
As the number of stacked memory cells increases, the thickness of the cells grows, making etching difficult and leading to reduced operational speed due to coupling capacitance between word lines, which can result in read operation errors.
Innovation Solution
A semiconductor device with air gaps of low permittivity interposed between word lines, and charge trap patterns formed only on the surfaces of the word lines, reducing coupling between adjacent word lines and memory cells, thereby preventing errors even at reduced thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of stacked memory cells is reduced to maintain operational speed, then coupling capacitance between word lines increases causing read operation errors, but reducing thickness further improves integration density
Solution Approach 1:
Air gaps are introduced as intermediary structures between adjacent word lines to reduce coupling capacitance. The air gap acts as a dielectric mediator with lower permittivity than conventional insulating materials, thereby reducing capacitive coupling while maintaining physical proximity for high integration density
Solution Approach 2:
The permittivity parameter of the dielectric material between word lines is changed from conventional high-k insulating materials to air (permittivity ≈ 1). This parameter change reduces the coupling capacitance between adjacent word lines, preventing read operation errors while maintaining thin cell structure
2Ease of manufacture
If charge trap patterns are formed only on word line surfaces rather than filling entire air gaps, then manufacturing complexity is reduced and etching difficulty is minimized, but coupling suppression effectiveness may be compromised
Solution Approach 1:
Charge trap patterns are formed locally only on the surfaces of word lines rather than filling the entire air gap volume. This local placement provides sufficient charge trapping capability to suppress coupling effects while avoiding the manufacturing complexity of forming and filling deep air gap structures
Solution Approach 2:
The charge trap structure is segmented into discrete patterns formed on word line surfaces rather than a continuous filling material. This segmentation simplifies the manufacturing process by eliminating the need for complex air gap filling while maintaining effective coupling suppression through distributed charge trapping sites
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses coupling between word lines and memory cells, maintaining operational speed and preventing read operation errors by using air gaps and strategically placed charge trap patterns, even as the thickness of the stacked layers decreases.
Implementation Method 1
Each air gap of a plurality of air gaps is interposed between two adjacent word lines... effectively suppresses coupling between word lines and memory cells
Implementation Method 2
Air gaps of low permittivity interposed between word lines... reducing coupling between adjacent word lines
Implementation Method 3
The charge trap pattern is interposed only between the first side surface and the channel structure... A first charge trap pattern is interposed between the first word line and the channel structure
Data Source
AI summary
A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure.