Vertical-Channel Semiconductor Device With Integrated Bit/Word Contacts
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing integration density, improving operation speed, and enhancing production yield and reliability due to the need for additional interconnection layers that increase device size and degrade electrical characteristics.
Innovation Solution
The semiconductor device incorporates vertical channel transistors with integrated bit line and word line contacts directly on the cell array region, eliminating the need for additional interconnection layers, thereby reducing device size and improving electrical and reliability characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional interconnection layers are added to connect bit lines and word lines, then electrical connection is achieved, but device size increases and electrical characteristics degrade
Solution Approach 1:
The patent merges the functions of bit line contacts and word line contacts into a single contact structure that simultaneously connects to both bit lines and word lines. This integration eliminates the need for separate interconnection layers, reducing device size while maintaining electrical connection reliability.
Solution Approach 2:
The contact structure is designed to serve multiple functions: it acts as both a bit line contact and a word line contact, and also serves as a bonding pad for external connections. This multi-functionality reduces the number of required interconnection layers and improves electrical characteristics by eliminating unnecessary interfaces.
2Ease of manufacture
If conventional interconnection structures are used, then bit lines and word lines are connected, but fabrication cost increases due to additional layers
Solution Approach 1:
The patent combines multiple interconnection functions into a single integrated contact structure, reducing the number of fabrication layers required. This simplification directly reduces fabrication cost while maintaining the necessary electrical connections.
Solution Approach 2:
The patent extracts and eliminates unnecessary intermediate interconnection layers from the conventional structure, keeping only the essential contact structure that performs multiple functions. This reduction in layers simplifies the fabrication process and lowers costs.
3Reliability
If more interconnection layers are added, then electrical connection reliability improves, but device complexity increases
Solution Approach 1:
The contact structure is designed to perform multiple functions simultaneously - serving as bit line contact, word line contact, and bonding pad. This multi-functionality reduces the number of required interconnection layers while maintaining or improving electrical connection reliability through better integration.
Solution Approach 2:
The patent merges separate contact structures into a single integrated contact that handles multiple connections. This consolidation reduces device complexity by eliminating unnecessary layers and interfaces while improving reliability through reduced points of failure.
Data Source
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AI summary
A semiconductor device may include a substrate including a cell array region, data storage patterns on the cell array region and spaced apart from each other in a first direction and a second direction that are parallel to a top surface of the substrate, word lines on the data storage patterns, extending in the second direction, and spaced apart from each other in the first direction, bit lines on the word lines to cross the word lines, extending in the first direction, and spaced apart from each other in the second direction, an insulating pattern on the bit lines, bit line contacts in the insulating pattern and electrically connected to the bit lines, respectively, and word line contacts in the insulating pattern between the bit lines and electrically connected to the word lines, respectively. The bit line contacts and the word line contacts may be on the cell array region.