Vertical Channel Semiconductor Device Bit-Line Leakage Reduction
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Solution Overview
Problem
Highly integrated semiconductor devices face challenges with bit-line junction leakage and increased parasitic capacitance due to the close proximity of gate electrodes and bit lines, which hinders their fabrication and performance.
Innovation Solution
A vertical-channel semiconductor device is designed with insulation films extending to the lower portions of buried bit-lines, reducing coupling capacitance and preventing bit-line junction leakage by forming an air-gap between the bit-lines and the substrate, thereby blocking conductive paths and enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the physical distance between bit lines is reduced to increase integration density, then device integration is improved, but bit-line junction leakage and parasitic capacitance increase
Solution Approach 1:
The bit line structure is segmented into multiple portions with insulation films inserted between them. This segmentation divides the continuous conductive path into isolated sections, preventing leakage current from propagating along the bit line while maintaining compact spacing for high integration density.
Solution Approach 2:
Insulation films are introduced as intermediary elements between adjacent bit line portions. These insulation films act as mediators that electrically isolate the bit lines, reducing parasitic capacitance and preventing junction leakage without requiring increased physical separation distance.
2Productivity
If the physical distance between gate electrodes is reduced to increase integration density, then device integration is improved, but bridge occurrence and parasitic capacitance increase
Solution Approach 1:
Insulation films serve as intermediary layers between closely spaced gate electrodes and bit lines. These intermediary insulation layers reduce the electric field coupling between adjacent conductors, thereby minimizing parasitic capacitance effects while allowing the gate electrodes to remain in close proximity for high integration.
3Reliability
If insulation films are extended to lower portions of buried bit-lines, then bit-line junction leakage is prevented, but device complexity increases
Solution Approach 1:
The insulation film formation process is merged with existing manufacturing steps such as spacer formation or interlayer insulation deposition. By combining multiple functions into a single integrated process flow, the leakage prevention capability is added without proportionally increasing overall device complexity.
Solution Approach 2:
The vertical extent parameter of the insulation films is optimized to extend only to the necessary depth for leakage prevention rather than full bit line depth. This parameter adjustment provides sufficient leakage blocking while minimizing the added structural complexity and material usage.
Data Source
AI summary
A vertical-channel semiconductor device includes an active pillar including a channel region, a gate located at a sidewall of the active pillar, a buried bit-line formed below the active pillar, and an insulation film formed below the buried bit-line. Some parts of the buried bit-line are replaced with an insulation film, such that a bit-line junction leakage is prevented.