Vertical Channel Memory Cell Layout for Higher Integration Density
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Solution Overview
Problem
The limited degree of integration in two-dimensional memory devices due to the expense of fine pattern formation technology and the restricted chip area hinders the economic feasibility and performance of semiconductor devices.
Innovation Solution
The semiconductor device incorporates a vertical channel transistor with various widths and forms of active patterns, including bit lines, active patterns, back gate electrodes, and word lines, arranged in a symmetrical and protruded configuration to enhance integration and miniaturization, with the active patterns having rounded edges and gate insulating patterns surrounding them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fine pattern formation technology is used to increase the degree of integration of two-dimensional memory devices, then the degree of integration is improved, but the manufacturing cost increases due to expensive equipment requirements
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertical channel transistors. The vertical channel extends in the third dimension (depth) rather than relying solely on planar scaling, enabling higher integration without requiring proportionally more expensive fine pattern formation processes. The active pattern forms a vertical channel that rises from the substrate, with the gate electrode wrapping around it, creating a 3D structure that improves integration while using relatively standard fabrication techniques.
2Productivity
If the area of unit memory cells is reduced to increase the degree of integration, then the degree of integration is improved, but the chip die area becomes more restricted
Solution Approach 1:
The vertical channel transistor utilizes the third dimension (vertical depth) to increase functionality within a smaller footprint on the chip surface. By extending the channel vertically rather than horizontally, the design packs more transistor capacity into the same planar area, effectively increasing integration density without proportionally reducing the usable chip die area.
Solution Approach 2:
The gate electrode is configured to wrap around or surround the vertical channel in a nested arrangement. The insulating layer is positioned between the gate electrode and the vertical channel, creating a nested structure where the gate envelops the channel. This nested configuration maximizes the use of vertical space and improves electrical control while maintaining a compact footprint.
Data Source
AI summary
A semiconductor device includes a substrate, a bit line extending in a first direction on the substrate, a first active pattern and a second active pattern on the bit line, a back gate electrode extending in a second direction perpendicular to the first direction across the bit line, and a word line extending in the second direction, wherein the first active pattern and the second active pattern have a minor symmetrical shape with respect to the back gate electrode when viewed in a third direction perpendicular to the first direction and the second direction.