Vertical Channel Structure Layout for Integrated Circuit Cell Design

Solution Overview

Problem

In the field of semiconductor manufacturing, there is a challenge in reducing the size of patterns and cells in integrated circuits while maintaining effective performance, particularly in designing integrated circuits with vertical channel transistors that require precise layout and spacing to enhance performance and reduce area usage.

Innovation Solution

The development of integrated circuits with a layout that includes adjacent cells featuring vertical channel structures, where the distance between these structures is carefully controlled to optimize spacing and connectivity, including the use of fin regions, vertical channel structures, gate electrodes, and source/drain regions, to form efficient transistors and connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the size of patterns and cells is reduced, then area efficiency is improved, but manufacturing precision and layout accuracy become more difficult to maintain

Engineering Contradiction:

Improvecell sizeVSAvoidlayout precision

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The cell is divided into multiple identical half-cell units (first half-cell and second half-cell) that are mirror images of each other. Each half-cell contains a standardized set of vertical channel structures, gate electrodes, and source/drain regions. This segmentation allows the overall cell size to be reduced while maintaining consistent spacing and precision within each modular unit, as the repetitive pattern simplifies manufacturing control.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The layout employs symmetric arrangement of vertical channel structures within each half-cell, where the first and second vertical channel structures are positioned at equal distances from their respective fin regions. This controlled symmetry ensures that spacing parameters remain consistent and predictable, facilitating precise manufacturing even as overall cell dimensions are reduced.

Inventive Principle:

Principle #4Asymmetry

2Area of stationary object

If vertical channel structures are placed closer together, then area efficiency is improved, but spacing control and connectivity become more challenging

Engineering Contradiction:

Improvecell areaVSAvoidspacing precision

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The cell is divided into multiple identical half-cell units (first half-cell and second half-cell) that are mirror images of each other. Each half-cell contains a standardized set of vertical channel structures, gate electrodes, and source/drain regions. This segmentation allows the overall cell size to be reduced while maintaining consistent spacing and precision within each modular unit, as the repetitive pattern simplifies manufacturing control.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The layout specifies precise spacing parameters: the distance between adjacent fin regions is equal to the distance between vertical channel structures within the same fin region. This standardized parameter approach ensures uniform spacing control across the entire cell, enabling tighter packing while maintaining manufacturing precision through consistent dimensional relationships.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If more vertical channel structures are added to increase transistor density, then device functionality is improved, but layout complexity increases

Engineering Contradiction:

Improvetransistor densityVSAvoidlayout complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The cell is divided into multiple identical half-cell units (first half-cell and second half-cell) that are mirror images of each other. Each half-cell contains a standardized set of vertical channel structures, gate electrodes, and source/drain regions. This segmentation allows the overall cell size to be reduced while maintaining consistent spacing and precision within each modular unit, as the repetitive pattern simplifies manufacturing control.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first and second half-cells are designed as universal, interchangeable units that can be replicated and combined to form complete cells. The symmetric arrangement allows the same structural pattern to serve multiple functional purposes: defining vertical channel positions, establishing gate electrode spacing, and determining source/drain region locations. This universality reduces layout complexity by using a single design template repeatedly.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11626516B2Integrated circuitry including vertical channel structure and layout method of the same

Publication Date: 2023.04.11 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is an integrated circuit implemented by a plurality of vertical field effect transistors (VFETs) in one or more semiconductor cells, wherein a distance between a pair of second vertical channel structures of a first cell and an adjacent pair of first vertical channel structures in a second cell, all facing a cell boundary between the first and second cells, is the same as a distance between the pair of the first vertical channel structures and a pair of second vertical channel structures arranged next to the pair of the first vertical channel structures in the first cell.