Vertical Channel Memory Cell Plug Structure for Compact Contacts
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity while maintaining good electrical characteristics and minimizing the area occupied by connection regions.
Innovation Solution
The semiconductor device incorporates a cell structure with gate electrodes and mold insulating layers alternately arranged, a channel structure penetrating through the gate electrodes, and insulating spacers between the cell plug and the gate electrodes, allowing for a stair-free contact structure that minimizes the connection region area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional contact structures are used to connect cell plugs to gate electrodes, then electrical connection is achieved, but the connection region occupies large area and integration is reduced
Solution Approach 1:
The patent transitions from a planar contact structure to a three-dimensional structure by having the cell plug extend vertically through multiple gate electrodes and mold insulating layers. This vertical arrangement in the first direction perpendicular to the substrate allows electrical connection while minimizing the horizontal footprint of the connection region, thereby improving integration density.
Solution Approach 2:
The cell plug is positioned within a structure where multiple gate electrodes and mold insulating layers are alternately stacked. The insulating spacers are formed on the sidewall of the cell plug, creating a nested configuration where the cell plug is surrounded by alternating conductive and insulating layers, enabling compact vertical integration.
2Quantity of substance
If vertical channel structure is implemented to increase storage capacity, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The vertical channel structure is segmented into multiple discrete gate electrodes stacked in the first direction, with mold insulating layers between them. This segmentation allows independent control of different memory cells within the same vertical column, enabling high storage capacity while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The alternating stack of gate electrodes and mold insulating layers serves multiple functions: gate electrodes provide electrical control for memory operations, while mold insulating layers provide both electrical isolation and structural support. This multi-functional design reduces the need for additional dedicated structures, thereby controlling device complexity.
3Reliability
If insulating spacers are added between cell plug and gate electrodes, then electrical characteristics are improved, but manufacturing complexity increases
Solution Approach 1:
The insulating spacers are formed through a self-aligned process where material is deposited on the sidewall of the cell plug and then anisotropically etched back. This self-aligned formation ensures precise positioning of the insulating spacers relative to the cell plug and gate electrodes without requiring additional alignment steps, thereby improving electrical characteristics while minimizing manufacturing complexity.
Data Source
AI summary
A semiconductor device is provided, including a peripheral circuit structure, and a cell structure on the peripheral circuit structure and including a cell region and a connection region. The cell structure includes gate electrodes and mold insulating layers alternately in a first direction in the cell region and the connection region, a channel structure penetrating through the gate electrodes and extending in the first direction, a cell plug contacting a first gate electrode among the gate electrodes in the connection region and penetrating through second gate electrodes below the first gate electrode among the gate electrodes, and insulating spacers on a sidewall of the cell plug and spaced apart from each other in the first direction, each of the insulating spacers between each of the second gate electrodes and the sidewall of the cell plug.