3D Vertical Channel Memory With Core-Bias Electrode for Lower Power
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Solution Overview
Problem
Existing three-dimensional semiconductor devices face challenges in achieving a narrow cell current range with a small ΔIcell/Icell ratio, leading to high power consumption, and require improvements in subthreshold swing (SS) without affecting threshold voltage width.
Innovation Solution
A semiconductor device comprising a core-bias electrode surrounded by a vertical semiconductor channel and a semiconductor channel, connected to a source line, functions as a back gate to increase SS without affecting threshold voltage width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional three-dimensional semiconductor devices are used, then device structure is simple, but subthreshold swing is insufficient leading to high power consumption
Solution Approach 1:
The patent implements a nested structure where the core-bias electrode is positioned at the center, surrounded by the dielectric core, which is in turn surrounded by the vertical semiconductor channel. This concentric nesting arrangement allows the core-bias electrode to effectively control the channel potential in the subthreshold regime, improving subthreshold swing and reducing power consumption without requiring complex external control circuits.
Solution Approach 2:
The patent transitions from planar gate control to three-dimensional radial control by positioning the core-bias electrode at the center of the vertical channel. This dimensional change enables the bias electrode to control the channel potential radially from the center, providing superior electrostatic control and subthreshold swing characteristics compared to conventional planar structures.
2Quantity of substance
If conventional structures are used, then manufacturing process is simple, but cell current range is wide leading to high power consumption
Solution Approach 1:
The nested concentric structure with the core-bias electrode at the center provides precise control over the cell current range. The radial field effect from the central electrode enables narrow current modulation, achieving a tight cell current range that reduces power consumption while maintaining compatibility with standard semiconductor manufacturing processes.
Solution Approach 2:
The patent utilizes parameter changes in the core-bias electrode voltage to precisely control the channel potential and modulate the cell current range. By adjusting the bias voltage parameter, the device achieves narrow current range control optimized for low power consumption applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The core-bias electrode enhances the subthreshold swing, reducing power consumption by controlling the channel potential in the subthreshold regime, thereby achieving a narrow cell current range.
Implementation Method 1
the core-bias electrode surrounded by the dielectric core and functions as a back gate to increase SS without affecting threshold voltage width
Data Source
AI summary
A semiconductor device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel that is laterally surrounded by the memory film, a drain region contacting a first end portion of the vertical semiconductor channel, a dielectric core surrounded by the vertical semiconductor channel, and a core-bias electrode surrounded by the dielectric core. A source layer contacts a second end portion of the vertical semiconductor channel and an end portion of the core-bias electrode.