Vertical Channel DRAM Cell With Assisted Gate Bit Line Control
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Solution Overview
Problem
Conventional dynamic random access memory (DRAM) devices with vertical transistors face issues such as high resistance in embedded bit lines, complex fabrication processes, and severe coupling noise between adjacent bit lines, which hinder performance and size reduction.
Innovation Solution
The implementation of a dynamic random access memory cell and array with vertical channel transistors, featuring semiconductor pillars, drain layers, assisted gates, control gates, and capacitors, where assisted gates are used to control the resistance and height of embedded bit lines, reducing coupling noise and simplifying fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If doped regions are used to form embedded bit lines, then the fabrication process is simple, but the resistance is high and device performance is poor
Solution Approach 1:
The patent changes the material parameter of the embedded bit line from doped semiconductor region to metal material, which fundamentally alters the electrical resistance characteristic. This parameter change enables low resistance while maintaining fabrication compatibility through metal deposition processes.
2Reliability
If doping concentration and doping depth are increased to lower resistance of embedded bit lines, then the resistance decreases, but the fabrication becomes more difficult
Solution Approach 1:
Instead of adjusting doping parameters (concentration and depth), the patent changes the fundamental material parameter from semiconductor to metal. This achieves low resistance without increasing fabrication complexity, as metal deposition is a standard semiconductor manufacturing process.
3Reliability
If metal embedded bit lines are formed, then the resistance is lowered and device performance is enhanced, but the fabrication process becomes complicated
Solution Approach 1:
The patent designs the metal embedded bit line structure to serve multiple functions: it acts as both the bit line conductor and provides mechanical support for the vertical transistor. This multi-functionality reduces the need for additional structural elements, thereby simplifying the overall fabrication process despite using metal materials.
4Speed
If vertical transistors are used in DRAM, then the channel length is reduced for faster operation, but severe short channel effect and on current reduction occur
Solution Approach 1:
The patent transitions from horizontal channel configuration to vertical channel configuration. This dimensional change allows the channel to extend in the vertical direction while maintaining adequate channel length for proper transistor control, thus avoiding short channel effects while still enabling compact device layout for fast operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration lowers the resistance of embedded bit lines, prevents coupling noise, and enhances device performance while allowing for size reduction, thereby improving the operational efficiency and ease of fabrication of DRAM devices.
Implementation Method 1
separated from the active region by a gate dielectric layer
Implementation Method 2
a capacitor, electrically connected to the source layer
Data Source
AI summary
A dynamic random access memory cell having vertical channel transistor includes a semiconductor pillar, a drain layer, an assisted gate, a control gate, a source layer, and a capacitor. The vertical channel transistor has an active region formed by the semiconductor pillar. The drain layer is formed at the bottom of the semiconductor pillar. The assisted gate is formed beside the drain layer, and separated from the drain layer by a first gate dielectric layer. The control gate is formed beside the semiconductor pillar, and separated from the active region by a second gate dielectric layer. The source layer is formed at the top of the semiconductor pillar. The capacitor is formed to electrical connect to the source layer.