Vertical Channel GAA Transistor Layout for Compact DRAM Cells
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Solution Overview
Problem
The design of dynamic random-access memory (DRAM) cells with planar transistors results in larger cell sizes due to the need for long channels to reduce leakage, which occupies valuable chip area.
Innovation Solution
The integration of vertical channel transistors in a semiconductor device, allowing for a 1T1C memory structure with reduced transistor area by fabricating thin-film transistors (TFTs) in the back-end-of-line (BEOL) process, utilizing oxide semiconductors like indium gallium zinc oxide (IGZO), and employing a stacked-capacitor design with vertical channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar transistors are used in DRAM cells, then leakage is reduced by having a long channel, but the transistor area and cell size increase
Solution Approach 1:
The patent transitions from planar (2D) transistor channels to vertical (3D) channels that extend in the depth direction perpendicular to the substrate. This dimensional change allows the channel length to extend vertically rather than horizontally, enabling long channels for low leakage while minimizing the horizontal footprint and cell area.
Solution Approach 2:
The patent implements gate electrodes that wrap around and surround the vertical channels in a nested configuration. The gate structure is positioned circumferentially around the channel, creating a gate-all-around (GAA) architecture where the gate electrode envelops the channel from multiple directions, enhancing control while maintaining compact area.
2Area of stationary object
If vertical channel transistors are used, then transistor area is reduced, but manufacturing complexity increases due to BEOL process integration
Solution Approach 1:
The patent divides the manufacturing process into distinct front-end-of-line (FEOL) and back-end-of-line (BEOL) stages. The vertical channel structures are formed during FEOL, while the gate electrodes are formed during BEOL. This segmentation allows each process stage to be optimized independently and enables integration of complex 3D structures using established manufacturing flows.
Solution Approach 2:
The patent forms the vertical channel structures and preliminary gate electrode patterns during the FEOL process before proceeding to BEOL. This preliminary action prepares the substrate with pre-formed vertical channels, simplifying subsequent BEOL gate formation and reducing overall manufacturing complexity by breaking down the complex integration into preparatory and finalization stages.
Data Source
AI summary
A semiconductor device includes a transistor that is disposed on a substrate. The transistor includes a gate electrode located over the substrate, a gate dielectric disposed on the gate electrode, a channel layer disposed on the gate dielectric, a first source/drain contact disposed on the channel layer and located on a side of the channel layer that is opposite to the substrate, and a second source/drain contact disposed on the channel layer and located on a side of the channel layer that faces the substrate. One of the gate dielectric and the channel layer at least partially surrounds the other one of the gate dielectric and the channel layer. A region of the channel layer between the first source/drain contact and the second source/drain contact is elongated in a direction perpendicular to the substrate.