Vertical Channel DRAM Cell Layout for Dense Memory Integration
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electrical characteristics and increased integration density in semiconductor memory devices.
Innovation Solution
A semiconductor device configuration featuring vertical channel transistors with improved electrical characteristics, including a first conductive line, second conductive lines, contact plugs, gate electrodes, semiconductor patterns, and gate insulating patterns, allowing for easy control of transistor operations and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If MOS-FETs are scaled down to reduce pattern size and design rule, then integration density increases, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar transistors to vertical channel transistors, changing the channel orientation from horizontal to vertical. This dimensional change allows the channel to extend in the vertical direction while maintaining a compact footprint on the substrate, thereby increasing integration density without deteriorating operational properties. The vertical channel structure enables better control over the channel region and improved electrical characteristics despite reduced pattern size.
Solution Approach 2:
The patent implements a multi-layered structure where conductive lines, contact plugs, gate electrodes, and semiconductor patterns are nested vertically. The gate electrode is positioned on contact plugs that connect to underlying conductive lines, creating a stacked configuration. This nesting approach maximizes the use of vertical space, allowing multiple functional elements to occupy the same horizontal footprint while maintaining proper electrical connections and control.
2Reliability
If vertical channel transistors are implemented to improve electrical characteristics, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the transistor structure into distinct vertical segments: substrate, conductive lines, contact plugs, gate electrodes, semiconductor patterns, and interlayer insulating layers. Each segment performs a specific function and can be fabricated using standardized processes. This segmentation allows for modular manufacturing where each layer is formed independently, then combined through alignment and patterning steps, making the complex vertical structure manageable through systematic process decomposition.
3Area of stationary object
If integration density is increased through vertical channel transistors, then area utilization improves, but control of transistor operations becomes more difficult
Solution Approach 1:
The patent designs the vertical channel transistor structure to serve multiple functions simultaneously. The gate electrode provides both the control function for the transistor operation and acts as a structural element in the vertical stack. The contact plugs serve both as electrical connections and as alignment references for subsequent patterning steps. This multi-functionality reduces the need for additional control structures, simplifying the overall device operation despite high integration density.
Data Source
AI summary
A semiconductor device includes a substrate having a pair of second conductive lines thereon, and a first conductive line extending between the pair of second conductive lines and the substrate. A contact plug extends between the pair of second conductive lines and is electrically connected to the first conductive line. A gate electrode extends on the contact plug. First and second semiconductor patterns extend on first and second ones of the pair of second conductive lines, respectively. A gate insulating pattern extends between each of the first and second semiconductive patterns and the gate electrode. The first conductive line may be configured as a word line, and the pair of second conductive lines may be configured as a pair of bit lines. The gate electrode may be configured as a gate electrode of a first access transistor within a first DRAM cell and as a gate electrode of a second access transistor within a second DRAM cell.