Vertical Channel DRAM Cell Layout With Overlapped Dual Word Lines
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Solution Overview
Problem
Shrinking word lines and bit lines in DRAM devices to enhance integration density leads to increased resistance and interference between memory cells, compromising high-speed performance and data retention.
Innovation Solution
Overlapping a vertical channel transistor with two word lines to reduce spacing without compromising width, allowing selection of one memory cell by two word lines and preventing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If word lines and bit lines are shrunk to enhance integration density, then the footprint of DRAM cells is reduced, but resistance increases and interference between memory cells worsens
Solution Approach 1:
The patent transitions from planar transistor architecture to vertical channel transistor architecture, moving the channel structure into the third dimension. The vertical channel extends perpendicular to the substrate surface, allowing word lines to overlap with the channel from above, thereby reducing the lateral footprint while maintaining effective channel control and reducing interference between adjacent memory cells.
Solution Approach 2:
The patent implements a nested structure where the vertical channel transistor is positioned within the memory cell footprint, and word lines are overlapped above the channel. This nesting arrangement allows multiple functional elements to occupy overlapping spatial regions, maximizing integration density without increasing the lateral cell size.
2Area of stationary object
If word lines are shrunk to reduce spacing, then integration density increases, but word line width is compromised affecting high-speed performance
Solution Approach 1:
By moving to vertical channel architecture, the word lines can be positioned above the channel in the vertical dimension rather than requiring lateral separation. This allows reduced spacing between word lines while maintaining adequate width for high-speed signal transmission, as the overlapping vertical configuration provides effective gate control without lateral crowding.
3Area of stationary object
If vertical channel transistor is overlapped with two word lines, then spacing between word lines is reduced, but device complexity increases
Solution Approach 1:
The vertical channel transistor is segmented into distinct regions including the channel portion extending vertically, source/drain regions at different heights, and gate structures. This segmentation allows the channel to be overlapped by multiple word lines at different vertical positions, achieving reduced spacing while managing complexity through modular structural divisions.
Data Source
AI summary
A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a bit line extending in a first direction, a first word line extending in a second direction and disposed over the bit line, and a second word line extending in the second direction and disposed over the bit line. The semiconductor device also includes a first pillar structure overlapping the first word line and the second word line.