Vertical-Channel Ferroelectric Flash Memory Cell Architecture
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Solution Overview
Problem
Current nonvolatile memory technologies based on ferroelectric FETs face challenges in achieving high density and low power operation effectively.
Innovation Solution
A 2T vertical ferroelectric memory cell architecture is developed, comprising a vertical select transistor and a vertical ferroelectric memory transistor in series between a bit line and a reference line, utilizing ferroelectric material like hafnium oxide, with a gate-all-around or single gate structure, and implemented in a stack configuration with select gate lines and word lines, allowing for high density and low power operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional ferroelectric FET memory architecture is used, then nonvolatile memory function is achieved, but high density and low power operation cannot be effectively realized
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to vertical 3D architecture, stacking select gate lines and word lines in multiple layers with vertical channel structures extending through them. This dimensional change enables higher memory density by utilizing the third dimension (vertical stacking) while maintaining manageable device complexity through systematic layering and modular cell design.
2Use of energy by moving object
If conventional ferroelectric FET memory architecture is used, then nonvolatile memory function is achieved, but low power operation cannot be effectively realized
Solution Approach 1:
The patent extracts and eliminates redundant transistors from the memory cell structure, achieving a minimal 2T (two-transistor) configuration per cell. By removing unnecessary active components while retaining the essential ferroelectric memory function, the design reduces power consumption and simplifies the circuit, thereby improving energy efficiency without compromising operational reliability.
3Quantity of substance
If vertical channel structures with gate-all-around structure are used, then memory density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the memory array into multiple stacked layers, with select gate lines in a first layer and word lines in a second layer, each layer being independently formed and controlled. This segmentation allows for modular manufacturing processes, where each layer can be fabricated with standard precision requirements, avoiding the need for ultra-precise single-step formation of the entire vertical structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 2T vertical ferroelectric memory technology operates with low power and high speed, is resistant to over-erase and over-program conditions, and can be integrated into high-density integrated circuits with reduced die size, enabling efficient logic circuitry integration.
Implementation Method 1
ferroelectric material is disposed at cross-points between the vertical channel structure and the corresponding word line
Implementation Method 2
A gate dielectric material is disposed at cross-points between the vertical channel structure and the corresponding select gate line
Data Source
AI summary
A device based on 2T vertical ferroelectric memory cells includes a plurality of select gate lines in a first layer, and a plurality of word lines in a second layer, with a plurality of vertical channel structures disposed operably with the select gate lines and word lines. A vertical channel structure of a memory cell in the plurality is disposed orthogonally relative to a corresponding select gate line and a corresponding word line, and forms a channel for the vertical select transistor and the vertical ferroelectric memory transistor. Ferroelectric material is disposed at cross-points between the vertical channel structure and the corresponding word line. A gate dielectric material is disposed at cross-points between the vertical channel structure and the corresponding select gate line. A NOR architecture memory uses the 2T vertical ferroelectric memory cells.