Vertical Channel Flash Memory Contact Resistance Reduction
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Solution Overview
Problem
In flash memory devices with a vertical transistor structure, reducing the width of the channel region to increase integration leads to increased contact resistance between the channel region and the wire due to a reduced contact area.
Innovation Solution
A flash memory device with a vertical channel structure is designed, where the contact resistance between the channel region and the wire is reduced by increasing the contact area through a specific arrangement of the bit line and channel region, including a pillar-shaped channel region and a bit line that surrounds the channel region, with a recessed shape to enhance contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of the channel region is reduced to increase integration degree, then the integration degree increases, but the contact area between the channel region and wire is reduced, leading to increased contact resistance
Solution Approach 1:
The bit line is configured to surround the channel region in a three-dimensional arrangement, transitioning from a planar contact to a multi-dimensional contact structure. This allows the bit line to contact the channel region at multiple locations including the upper surface and side walls, effectively increasing the contact area without expanding the planar footprint, thus resolving the contradiction between integration density and contact resistance.
Solution Approach 2:
The bit line is positioned to surround and partially enclose the channel region, creating a nested configuration where the bit line encompasses the channel region. This nesting arrangement maximizes the contact interface between the two structures, providing extensive electrical contact while maintaining a compact vertical profile that supports high integration.
2Productivity
If the channel region width is reduced to increase integration degree, then the integration degree increases, but the electrical connectivity between channel region and wire deteriorates
Solution Approach 1:
The bit line extends vertically and surrounds the channel region, creating contact in multiple dimensions rather than a single planar interface. This multi-dimensional contact ensures robust electrical connectivity even when the channel region dimensions are reduced, as the surrounding configuration provides multiple parallel conduction paths that compensate for the reduced cross-sectional area.
3Device complexity
If a conventional planar wire contact is used, then the device structure is simple, but the contact area is insufficient leading to high contact resistance
Solution Approach 1:
The bit line is configured to surround the channel region, transitioning from a simple planar contact to a three-dimensional surrounding structure. This configuration increases the contact area by utilizing vertical and lateral surfaces of the channel region, thereby reducing contact resistance while maintaining a relatively straightforward fabrication process that builds upon conventional planar structures.
Data Source
AI summary
A flash memory device having a vertical channel structure. The flash memory device includes a substrate having a surface that extends in a first direction, a channel region having a pillar shape and extending from the substrate in a second direction that is perpendicular to the first direction, a gate dielectric layer formed around the channel region, a memory cell string comprising a plurality of transistors sequentially formed around the channel region in the second direction, wherein the gate dielectric layer is disposed between the plurality of transistors and the channel region, and a bit line connected to one of the plurality of transistors, and surrounding a side wall and an upper surface of one end of the channel region so as to directly contact the channel region.