Vertical Channel Flash Memory Pillars for Density and Isolation
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Solution Overview
Problem
As the density of flash memory devices increases, the area available for forming individual memory cells decreases, leading to reduced electron loading capacity and electrical coupling between adjacent floating gates, which affects cell write characteristics, and both NOR and NAND flash memory devices are limited by finite erase-write cycles, necessitating improved electrical isolation and endurance.
Innovation Solution
The development of semiconductor flash memory cells with a semiconductor substrate, source lines, semiconductor pillars, charge storage structures, trench isolation structures, and specific materials for tunnel, charge storage, and blocking layers, along with optimized pillar and trench configurations to enhance electrical isolation and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of flash memory devices is increased, then the memory cell density is improved, but the area available for forming individual memory cells decreases leading to reduced electron loading capacity and electrical coupling between adjacent floating gates
Solution Approach 1:
The patent transitions from planar memory cell structures to three-dimensional vertical channel structures with floating gates extending in the vertical dimension. This allows memory cells to be stacked above each other, increasing density while maintaining adequate horizontal spacing between cells to prevent electrical coupling and preserve electron loading capacity.
Solution Approach 2:
The patent divides the memory array into multiple independent blocks with separate floating gate structures for each cell. This segmentation isolates adjacent cells electrically, preventing coupling effects even at high densities, while allowing each cell to maintain its full electron loading capacity independently.
2Ease of manufacture
If conventional floating gate structures are used, then the manufacturing process is simpler, but the number of erase-write cycles is limited due to finite endurance
Solution Approach 1:
The patent employs composite material structures including multiple dielectric layers (tunnel dielectric, charge storage layer, blocking dielectric) with specific material compositions optimized for endurance. This composite structure distributes stress and degradation across multiple layers, extending the number of erase-write cycles beyond conventional single-layer floating gate structures.
Solution Approach 2:
The patent modifies critical parameters including the thickness of tunnel and blocking dielectric layers, the composition of charge storage materials, and the doping profiles in semiconductor regions. These parameter optimizations enhance the structural integrity and electrical performance under repeated programming and erasing operations, significantly improving device endurance.
3Area of stationary object
If adjacent floating gates are positioned closer together to increase density, then the memory cell area is reduced, but electrical coupling between adjacent floating gates increases affecting cell write characteristics
Solution Approach 1:
By positioning floating gates at different vertical levels and using vertical channel structures, the patent reduces the horizontal footprint of each memory cell. This allows cells to be packed more densely in the planar direction while maintaining sufficient vertical isolation to prevent electrical coupling, preserving write characteristics.
Solution Approach 2:
The patent introduces intermediate isolation structures including oxide-nitride-oxide (ONO) dielectric layers and lightly-doped semiconductor regions between adjacent floating gates. These intermediary elements act as electrical barriers that prevent coupling effects even when floating gates are positioned in close proximity, enabling higher density without degrading write characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves electrical isolation, increases memory cell density, and extends the number of erase-write cycles, addressing the limitations of existing flash memory technologies by enhancing the performance and durability of flash memory devices.
Implementation Method 1
a voltage differential is established between the CG and source sufficient to induce movement of the electrons from the FG to the source through a process referred to as quantum tunneling or Fowler-Nordheim (F-N) tunneling
Implementation Method 2
a voltage differential is established between the CG and source sufficient to induce movement of the electrons from the FG to the source through a process referred to as quantum tunneling or Fowler-Nordheim (F-N) tunneling
Implementation Method 3
NOR flash memory cells may be programmed by initiating electron flow between the source and drain and then applying a sufficiently large voltage to the CG to produce a electric field sufficient to draw electrons through the insulating material surrounding the FG, a process sometimes referred to as hot-electron injection
Data Source
AI summary
Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opposite side surfaces of the semiconductor pillar and separated by trench isolation structures. The x and y pitch separating adjacent semiconductor pillars in the memory cell array are selected whereby forming the trench isolation structures serves to separate both charge storage structures and conductive structures provided on opposite sides of a semiconductor pillars. Also disclosed are methods of fabricating such structures whereby the density of flash memory devices, particularly NOR flash memory devices, can be improved.