Vertical Channel GAA MOSFET Doping for Reliable Scaling
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Solution Overview
Problem
The increasing demand for high-performance semiconductor devices with high speed and multifunctionalization poses challenges in manufacturing fine patterns and reducing the limitations of planar metal oxide semiconductor FETs, particularly in achieving reliable operating characteristics due to the reduction in size.
Innovation Solution
A semiconductor device design featuring vertically spaced channel layers with a gate structure that intersects and surrounds the channel layers, incorporating impurities with varying concentrations to enhance electrical characteristics and reliability, including a multi-bridge channel FET structure with a gate-all-around field effect transistor configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of planar metal oxide semiconductor FET is reduced to achieve high integration, then the degree of integration increases, but the operating characteristics and reliability deteriorate
Solution Approach 1:
The patent transitions from a planar two-dimensional channel structure to a three-dimensional vertical channel structure by growing channel layers vertically on the active region. This dimensional change allows the device to achieve high integration density while maintaining reliable operating characteristics through the vertical field effect transistor configuration, where the gate electrode surrounds the vertical channel layers.
Solution Approach 2:
The patent implements non-uniform impurity distribution within the channel layers, with different impurity concentrations in lower regions adjacent to the active region versus upper regions. This local quality variation optimizes the electrical characteristics and reliability of the vertical channel structure, addressing the deterioration of operating characteristics that occurs with size reduction.
2Productivity
If fine patterns are implemented to achieve high integration, then the degree of integration increases, but the manufacturing precision requirements increase
Solution Approach 1:
By transitioning to vertical channel layers grown epitaxially on the active region, the patent achieves high integration density without requiring extremely fine lateral patterning. The vertical orientation allows channels to be stacked above each other, reducing the lateral footprint and thus the stringency of lateral pattern fabrication precision requirements.
3Reliability
If vertically spaced channel layers with varying impurity concentrations are used, then the electrical characteristics and reliability improve, but the device complexity increases
Solution Approach 1:
The patent applies local quality by introducing impurities at specific locations within the vertical channel layers - particularly in the lower regions adjacent to the active region - while keeping other regions relatively pure. This targeted impurity distribution improves electrical characteristics and reliability without requiring complex structures throughout the entire device, thus managing device complexity.
Data Source
AI summary
A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region and including a semiconductor material, a gate structure extending in a second direction on the substrate, and a source/drain region disposed on the active region on at least one side of the gate structure. The gate structure intersects the active region and the plurality of channel layers, and surrounds the plurality of channel layers. The source/drain region contacts the plurality of channel layers and includes first impurities. In at least a portion of the plurality of channel layers, a lower region adjacent to the active region includes the first impurities and second impurities at a first concentration, and an upper region includes the first impurities and the second impurities at a second concentration lower than the first concentration.