Vertical Channel Semiconductor Device Gate Contamination Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices with vertical channels face challenges in reducing contamination of epitaxial process equipment by gate electrode materials during the growth of semiconductor layers for source/drain regions, and in achieving improved resistance characteristics.
Innovation Solution
The semiconductor device design includes semiconductor fins with source/drain regions and gate electrodes disposed on the sides of these fins, with insulating layers covering the gate electrodes to prevent contamination and enhance resistance, featuring a vertical field effect transistor structure with a gate all around (GAA) configuration and selective epitaxial growth of semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate electrode material is used in vertical channel devices, then device performance is improved, but contamination of epitaxial process equipment occurs during semiconductor layer growth
Solution Approach 1:
A first insulating layer is introduced as an intermediary between the gate electrode and the epitaxial growth environment. This insulating layer acts as a protective barrier that prevents gate electrode material from contaminating the epitaxial process equipment during semiconductor layer growth, while still allowing the gate electrode to perform its function in controlling the vertical channel device.
2Object-generated harmful factors
If insulating layers are added to cover gate electrodes, then contamination is reduced, but device structure complexity increases
Solution Approach 1:
The first insulating layer is positioned to simultaneously achieve multiple functions: it covers and protects the gate electrode from contamination during epitaxial growth, and also serves as part of the overall device structure that defines the vertical channel geometry. This multi-functionality reduces the need for additional separate protective structures.
3Manufacturing precision
If selective epitaxial growth is used for source/drain regions, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
Selective epitaxial growth is applied specifically to the source/drain regions where precise dimensional control is critical, while other parts of the device use standard fabrication processes. This localized application of selective epitaxial growth achieves high manufacturing precision for the most critical dimensions without requiring the entire device manufacturing process to be overly complex.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces contamination of epitaxial process equipment and improves resistance characteristics of semiconductor devices by using insulating layers to protect the gate electrodes and allowing for selective growth of semiconductor layers, enhancing the performance of vertical channel devices.
Implementation Method 1
insulating layers contact the side surfaces of the semiconductor fins and cover upper surfaces of the gate electrode
Implementation Method 2
selective epitaxial growth of semiconductor layers
Data Source
AI summary
A semiconductor device includes a substrate and a plurality of semiconductor fins protruding from the substrate. Source/drain regions are disposed at tops of respective ones of the semiconductor fins, each having a width greater than a width of individual ones of the semiconductor fins. A gate electrode is disposed on side surfaces of the semiconductor fins below the source/drain regions. Insulating layers contact the side surfaces of the semiconductor fins and cover upper surfaces of the gate electrode.