Vertical Channel Gate Electrodes on Isolation Layers
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Solution Overview
Problem
Semiconductor devices with vertical channels face issues such as leakage current and short channel effects due to gate electrodes intersecting element isolation layers, making it difficult to form a contact shape or bar shape gate electrode pattern, especially as design rules decrease, leading to challenges in obtaining sufficient overlap margins during photolithography.
Innovation Solution
A method of manufacturing semiconductor devices with vertical channels involves etching semiconductor substrates to form protruding active regions, filling material layers in element isolation regions, and using line-shaped mask patterns to form gate electrodes on element isolation layers along a major axis, preventing leakage current and ensuring sufficient overlap margins through a damascene process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a gate electrode is formed to cover the element isolation layer along the major axis of the active region, then the channel length is increased and short channel effects are prevented, but leakage current is generated in adjacent portions of the active region
Solution Approach 1:
The gate electrode pattern is extracted or removed from the element isolation layer region. The patent specifically prevents the gate electrode from being formed on the element isolation layer 22 disposed along the major axis of the active region 12, thereby eliminating the source of leakage current while maintaining the vertical channel structure for improved current characteristics
Solution Approach 2:
The gate electrode formation is made local to specific regions. The patent forms gate electrodes only in certain areas while deliberately excluding the element isolation layer region, creating a non-uniform gate electrode distribution that prevents leakage current in specific locations while maintaining channel length in other areas
2Productivity
If the design rule is decreased to improve device integration, then the device density is increased, but it becomes difficult to form a contact shape or bar shape gate electrode pattern and obtain sufficient overlap margin
Solution Approach 1:
The gate electrode pattern is changed from a two-dimensional contact or bar shape to a one-dimensional line shape that extends in a specific direction. This dimensional simplification makes the pattern formation more robust against photolithography variations and allows sufficient overlap margin to be obtained even at reduced design rules
Solution Approach 2:
The gate electrode pattern geometry is changed from contact/bar shape to line shape, and the orientation is set at a predetermined angle (e.g., 45 degrees) with respect to the major axis of the active region. This parameter change in pattern shape and orientation provides better process margin and facilitates formation at reduced design rules
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents leakage current and enhances current characteristics by forming gate electrodes on element isolation layers, allowing for greater integration and improved pattern formation without the need for additional hard masks, thus addressing the challenges of short channel effects and parasitic capacitance.
Implementation Method 1
etching a semiconductor substrate to protrude a plurality of active regions that are adjacent to each other
Implementation Method 2
forming filling material layers in element isolation regions by filling etched portions between the active regions
Data Source
AI summary
A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.