Vertical Channel Semiconductor Structure With IGZO Charge Isolation
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Solution Overview
Problem
Current semiconductor devices face challenges in maintaining performance and preventing performance degradation due to trapped charges in vertical channel regions, particularly the floating body effect, which leads to leakage current and mutual interference between semiconductor patterns.
Innovation Solution
Incorporating a complementary structure with an oxide semiconductor layer that includes indium gallium zinc oxide (IGZO) or other oxide semiconductor materials with adjusted energy band gaps, positioned between single crystal semiconductor patterns to remove trapped charges and act as an insulator, thereby preventing performance degradation and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical channel regions are used in small-sized semiconductor elements, then device integration density is improved, but charge trapping occurs leading to performance degradation and leakage currents
Solution Approach 1:
An oxide semiconductor layer is introduced as an intermediary between the vertical channel regions to suppress charge trapping and eliminate leakage currents. This intermediary layer prevents direct interaction between adjacent semiconductor patterns, thereby maintaining performance stability while preserving high integration density.
Solution Approach 2:
The invention uses a composite structure combining conventional semiconductor materials for vertical channel regions with oxide semiconductor materials for the complementary structure. This composite approach leverages the high mobility of single crystal semiconductors while using oxide semiconductors to provide electrical isolation and prevent charge trapping.
2Productivity
If element sizes are reduced to improve performance, then device density is increased, but reliable formation of small-sized elements becomes difficult
Solution Approach 1:
The oxide semiconductor complementary structure acts as a mediator that enables reliable formation of small-sized elements by providing electrical isolation. This intermediary structure prevents interference between adjacent miniaturized elements, making it possible to reliably manufacture high-density devices.
3Reliability
If complementary structures are added to prevent charge trapping, then performance stability is improved, but device complexity increases
Solution Approach 1:
The oxide semiconductor complementary structure serves multiple functions simultaneously: it acts as an electrical isolator between adjacent patterns, suppresses charge trapping in vertical channel regions, and prevents leakage currents. This multi-functionality achieves performance stability without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The oxide semiconductor layer effectively removes trapped charges and prevents performance degradation caused by the floating body effect, enhancing the semiconductor device's reliability and reducing mutual interference between adjacent semiconductor patterns.
Implementation Method 1
the oxide semiconductor layer effectively removes trapped charges and prevents performance degradation caused by the floating body effect
Implementation Method 2
positioned between single crystal semiconductor patterns to remove trapped charges and act as an insulator, thereby preventing performance degradation and leakage current
Data Source
AI summary
A semiconductor device includes a first single crystal semiconductor pattern including a first source/drain region, a second source/drain region, and a first vertical channel region between the first source/drain region and the second source/drain region, the second source/drain region being at a higher level than the first source/drain region; a first gate electrode facing a first side surface of the first single crystal semiconductor pattern; a first gate dielectric layer, the first gate dielectric layer including a portion between the first single crystal semiconductor pattern and the first gate electrode; and a complementary structure in contact with a second side surface of the first single crystal semiconductor pattern, wherein the complementary structure includes an oxide semiconductor layer.