Vertical Channel Memory Device with Arc Segments

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Solution Overview

Problem

Current memory devices, such as DRAM and NAND flash, have a significant latency gap, leading to decreased data processing speed in computer systems, and existing storage-class memory (SCM) technologies do not meet requirements for high density, high access speed, and low latency.

Innovation Solution

A memory device with a drain pillar structure, source pillar structure, and two arc channel parts is manufactured using a method that forms a vertical channel structure and charge trapping structure within a hole, with the channel structure divided into arc channel parts by openings, and a gate structure surrounding the pillars and channel structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If DRAM type memory device is used, then access speed is improved, but memory density is limited and cost per bit is high

Engineering Contradiction:
Improveaccess speedVSAvoidmemory density
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent transitions from planar 2D memory architecture to three-dimensional vertical channel architecture. The vertical channels extend in the depth direction from the substrate surface, utilizing the third dimension (Z-axis) to increase storage capacity without expanding the planar footprint. This dimensional transition enables higher memory density while maintaining fast access speeds characteristic of DRAM.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The memory device is segmented into multiple vertical channels, each containing distinct functional regions (charge trapping structure, first memory cell region, second memory cell region). Each vertical channel is further divided into multiple memory cells through word line separation, allowing independent addressing and access. This segmentation enables parallel operations and increases overall memory capacity within a compact form factor.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If NAND flash type memory device is used, then memory density is improved, but access speed is reduced and latency is high

Engineering Contradiction:
Improvememory densityVSAvoidaccess speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

Different regions within each vertical channel are assigned different functional qualities: the charge trapping structure provides non-volatile storage capability, the first memory cell region optimized for fast access, and the second memory cell region for additional capacity. This local differentiation allows the device to exhibit both high-speed DRAM-like access and high-density NAND flash-like storage in the same structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The memory device employs composite material structures including oxide-nitride-oxide stacks for charge trapping, alternating oxide and nitride layers for tunnel barriers and charge storage, and conductive materials for word lines and bit lines. These composite structures enable simultaneous achievement of fast write/read operations and high storage density by combining materials with complementary properties.

Inventive Principle:
Principle #40Composite materials

3Quantity of substance

If vertical channel structure with charge trapping structure is formed, then memory density is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvememory densityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The oxide-nitride-oxide charge trapping structure and alternating oxide-nitride memory cell region structures are formed as preliminary layers before vertical channel patterning. The tunnel oxide layers, charge trapping layers, and barrier layers are deposited in advance using atomic layer deposition (ALD), creating a pre-fabricated stack that simplifies subsequent vertical channel formation and reduces overall manufacturing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Traditional mechanical patterning methods are replaced with atomic layer deposition (ALD) for forming ultra-thin oxide and nitride layers with precise thickness control. ALD enables conformal coating of complex three-dimensional structures and provides atomic-level thickness precision, replacing multiple mechanical deposition and etching steps with a more efficient vapor-phase deposition process.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11069708B2Memory device and method for manufacturing the same
Publication Date: 2021.07.20 MACRONIX INTERNATIONAL CO LTD
  • US11069708B2 patent drawing
  • US11069708B2 patent drawing
  • US11069708B2 patent drawing

AI summary

A memory device and a method for manufacturing the same are provided. A memory device includes a drain pillar structure, a source pillar structure, a charge trapping structure, a vertical channel structure and a gate structure. The drain pillar structure is formed in a first opening. The source pillar structure is formed in a second opening. The vertical channel structure and the vertical channel structure are formed in a hole partially overlapping the first opening and the second opening. The vertical channel structure is divided into two arc channel parts by the drain pillar structure and the source pillar structure. The gate structure surrounds the drain pillar structure, the source pillar structure and the vertical channel structure.