Vertical Channel Memory Cell Structure for Low Leakage Density
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Solution Overview
Problem
Current non-volatile memory cells face issues with high current leakage leading to power consumption and reduced data retention due to the need for frequent refreshing, which decreases power efficiency and memory cell density.
Innovation Solution
A semiconductor memory cell structure with a vertical gate electrode and a cylindrical channel design that increases gate length without increasing horizontal or lateral size, reducing current leakage and enhancing power efficiency by allowing longer data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the gate length is increased to reduce current leakage, then power efficiency improves, but the horizontal or lateral size of the memory cell structure increases
Solution Approach 1:
The gate electrode is configured in a vertical direction extending from the substrate upward, transforming the gate length dimension from the horizontal plane to the vertical dimension. This allows the gate length to be increased for better leakage control without consuming additional horizontal area, directly resolving the technical contradiction between reducing current leakage and maintaining compact cell footprint.
2Duration of action of stationary object
If the gate length is increased to improve data retention, then data retention time increases, but the memory cell density decreases
Solution Approach 1:
By extending the gate electrode vertically rather than horizontally, the invention achieves longer gate lengths that provide improved data retention without increasing the lateral footprint of each memory cell. This vertical dimensionality change enables higher memory cell density while maintaining extended data retention capabilities.
3Loss of energy
If a vertical gate electrode with cylindrical channel is used to reduce current leakage, then power efficiency improves, but the device complexity increases
Solution Approach 1:
The channel is formed as a cylindrical structure wrapping around the vertical gate electrode, creating a curved three-dimensional path for charge carrier flow. This cylindrical geometry provides superior gate control over the channel and reduces current leakage more effectively than planar structures, achieving lower power consumption despite the increased structural complexity.
Data Source
AI summary
A semiconductor device includes a memory cell structure that includes a transistor structure and a storage structure. A gate electrode of the transistor structure extends in a direction that is approximately perpendicular to a surface of a substrate of the semiconductor device, which enables the gate length to be increased with minimal to no increase in horizontal or lateral size of the memory cell structure. A channel layer wraps around the sidewalls and the bottom surface of the gate electrode to form a cylindrical channel. This increases the channel area of the transistor structure, which enables a low current leakage to be achieved for the memory cell structure, and enables a high lateral density of memory cell structures to be achieved in the semiconductor device.