Vertical Channel Memory Device Reducing Etch Damage
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Solution Overview
Problem
Conventional non-volatile memory devices face challenges in reducing size and minimizing etch damage during channel layer formation, which affects storage density and operating characteristics due to horizontal floating gate and nitride layer structures, and the etching process used to form vertically oriented channel layers can cause damage and generate coupling effects between channel layers.
Innovation Solution
A memory device is manufactured with vertically formed channel layers and an ONO layer pattern on the sidewalls, using an epitaxial growth process to form channel layers without etching damage, and an insulating layer is used to fill the space between channel layers, leaving a void to reduce coupling effects, thereby improving operating characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If an etching process is employed to vertically form the channel layer, then the storage density is improved, but the channel layer suffers from etch damage
Solution Approach 1:
A sacrificial layer is introduced as an intermediary element that enables the vertical formation of channel layers through epitaxial growth. The sacrificial layer serves as a template that defines the vertical structure without causing etch damage to the channel layer material itself, thus resolving the contradiction between achieving high storage density through vertical structures and maintaining channel layer integrity
Solution Approach 2:
The mechanical etching process is replaced with an epitaxial growth process. Instead of removing material through etching to form vertical channel layers, the channel layers are grown vertically on the sacrificial layer through controlled deposition, eliminating etch damage while achieving the desired vertical structure for increased storage density
2Reliability
If a dielectric material with large dielectric constant is filled in the space between channel layers, then the coupling effect is reduced, but the device size increases
Solution Approach 1:
The insulating layer is applied selectively in specific locations - filling spaces between channel layers where coupling effects occur - rather than uniformly throughout the entire device. This localized application reduces coupling effects in critical areas without unnecessarily increasing overall device volume
Solution Approach 2:
The insulating layer is formed with controlled porosity or void spaces, allowing it to provide electrical isolation between channel layers while occupying minimal volume. The porous structure enables the material to reduce coupling effects without fully densifying the space between channels, thus avoiding excessive size increase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces etch damage and coupling effects between channel layers, enhancing the storage density and operational efficiency of non-volatile memory devices by forming channel layers using epitaxial growth and strategically placing an insulating layer to minimize interference.
Implementation Method 1
forming a pair of channel layers on both sidewalls of a sacrificial single crystalline layer pattern
Implementation Method 2
an insulating layer is used to fill the space between channel layers, leaving a void to reduce coupling effects
Data Source
AI summary
In a memory device and a method of manufacturing the memory device, a pair of channel layers included in the memory device may be formed on a sidewall of the sacrificial single crystalline layer pattern located on a protrusion of a semiconductor substrate. Accordingly, an etch damage may be reduced at the channel layer. The sacrificial single crystalline layer pattern may be removed to generate a void between the pair of the channel layers. As a result, a generation of a coupling effect may be reduced between the channel layers.