Vertical Channel Memory Device With Doped Isolation Regions
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Solution Overview
Problem
Conventional flash memory devices face challenges in increasing storage density due to programming disturbance and leakage issues, especially when scaling down cell length, and vertical channel cells suffer from electron punch-through and mutual perturbation.
Innovation Solution
A memory device with a substrate having trenches and doped regions, where the conductive layer fills the trenches, and charge storage layers are used between the substrate and conductive layer, allowing for six physical bits per memory cell, with sloped sidewalls and specific voltage applications for programming and erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the cell length of planar channel cell is scaled down to increase storage density, then storage density is improved, but programming disturbance and source/drain resistance worsen
Solution Approach 1:
The patent transitions from planar channel cells to vertical channel cells, changing the dimensional orientation of the channel from horizontal to vertical. This allows the channel to extend in the depth direction (z-axis) rather than along the surface (x-y plane), enabling increased storage density without reducing cell length in the planar direction, thereby avoiding programming disturbance and source/drain resistance issues associated with scaling.
Solution Approach 2:
The vertical channel cell is divided into multiple storage sites along the channel length, with first doped regions positioned at different heights. This segmentation allows independent control of multiple bits within a single vertical channel, achieving high storage density while maintaining proper isolation between storage sites to prevent programming disturbance.
2Quantity of substance
If vertical channel cells are used to increase bits per cell, then storage density is improved, but electron punch-through and leakage worsen
Solution Approach 1:
The patent introduces first doped regions with specific doping types and concentrations at particular positions along the vertical channel (adjacent to upper portions of trenches). These localized doped regions create potential barriers that prevent electron punch-through between bottom junctions, while maintaining the vertical channel structure for high storage density. Each local region has optimized properties to address specific issues at that location.
3Quantity of substance
If vertical channel cells are placed close together to increase density, then storage density is improved, but mutual perturbation and programming disturbance worsen
Solution Approach 1:
The patent introduces second doped regions positioned under the bottoms of trenches as intermediary structures between adjacent vertical channel cells. These second doped regions act as isolation elements that prevent mutual perturbation between neighboring cells while allowing the cells to be placed close together for high density. The intermediary doped regions provide electrical isolation without requiring large spacing between cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances storage density without mutual perturbation and programming disturbance, allowing for efficient data storage and retrieval in a 6-bit-per-cell memory device.
Implementation Method 1
Another type of the flash memory uses a charge-trapping structure, such as a layer of non-conductive SiN material, rather than the conductive gate material used in floating gate devices. When a charge-trapping cell is programmed, the charge is trapped and does not move through the non-conductive layer.
Implementation Method 2
The first doped regions are configured in the substrate adjacent to both sides of an upper portion of each trench, respectively. The second doped regions are configured in the substrate under bottoms of the trenches, respectively.
Data Source
AI summary
The memory device is described, which includes a substrate, a conductive layer, a charge storage layer, a plurality of first doped regions and a plurality of second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first doped regions are configured in the substrate adjacent to both sides of an upper portion of each trench, respectively. The first doped regions between the neighbouring trenches are separated from each other. The second doped regions are configured in the substrate under bottoms of the trenches, respectively. The second doped regions and the first doped regions are separated from each other, such that each memory cell includes six physical bits.