Vertical Channel Memory Block Erase Control via Floating Word Lines
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Solution Overview
Problem
As the number of memory cells in semiconductor memory devices increases to achieve high integration density, the size of memory blocks also grows, leading to compatibility issues with memory controllers due to fixed control limits, affecting the erase operation efficiency.
Innovation Solution
The semiconductor memory device employs a structure with a vertical channel layer and word lines at different heights, allowing for the logical size of memory blocks to be controlled by setting word lines to a floating state and applying precharge and erase voltages to manage hole supply and erase operations, thereby optimizing memory cell erasure without damaging source select transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells in a memory block is increased to achieve high integration density, then the storage capacity is improved, but the compatibility with memory controllers deteriorates due to fixed control limits
Solution Approach 1:
The patent divides the memory block into multiple sub-blocks that can be independently controlled. By segmenting the memory block, the system can perform erase operations on smaller units while maintaining compatibility with memory controllers that have fixed block size limitations, thus resolving the contradiction between increasing storage capacity and maintaining controller compatibility
Solution Approach 2:
The patent introduces dynamic control of word lines through floating state and ground state switching. This dynamic mechanism allows flexible selection of memory cells for erase operations, enabling the system to adapt to different controller requirements while maintaining high integration density
2Quantity of substance
If the size of the memory block is increased, then the storage capacity is improved, but the erase operation efficiency deteriorates due to fixed block control size
Solution Approach 1:
By segmenting the memory block into controllable sub-units, the system can perform erase operations more efficiently on smaller units rather than processing the entire large block, thus improving erase operation efficiency while maintaining high storage capacity
Solution Approach 2:
The patent applies preliminary action by setting word lines to floating state before erase operations and using precharge voltage to supply holes to the vertical channel layer in advance. This preliminary preparation enables faster and more efficient erase operations on large memory blocks
3Ease of operation
If word lines are set to floating state to supply holes to the vertical channel layer, then the erase operation is enabled, but parasitic capacitance effects increase
Solution Approach 1:
The patent applies local quality by selectively setting specific word lines to floating state while keeping others at ground state. This localized approach enables hole supply to specific regions for erase operations while minimizing parasitic capacitance effects in other areas, thus resolving the contradiction between erase operation capability and parasitic capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances compatibility between memory controllers and devices by allowing for efficient erasure of memory cells while maintaining transistor integrity, even with larger memory blocks, by logically reducing the memory block size and minimizing parasitic capacitance effects.
Implementation Method 1
supply holes to the vertical channel layer
Implementation Method 2
memory cells formed in portions where the word lines surround the vertical channel layer
Data Source
AI summary
A semiconductor memory device and a method of manufacturing the same are provided. The device includes a memory block and one or more peripheral circuits. The memory block includes a bit line, a common source line, a vertical channel layer coupled between the bit line and the common source line, word lines surrounding the bit line at different heights from a semiconductor substrate, and memory cells formed in portions where the word lines surround the vertical channel layer. The one or more peripheral circuits are configured to set the word lines to a floating state to supply holes to the vertical channel layer when a precharge voltage is applied to the common source line, and set word lines of memory cells to be erased to a ground state when an erase voltage is applied to the common source line.