Vertical Channel Nonvolatile Memory Fabrication for Integration Density
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Solution Overview
Problem
Conventional vertical channel type nonvolatile memory devices face limitations in integration density due to degraded layer quality of the tunnel insulation layer and challenges in forming single crystal silicon channels, leading to degraded data retention and current flow issues.
Innovation Solution
The method involves alternately forming sacrificial layers and interlayer dielectric layers over a substrate, etching to create openings for channel formation, and sequentially depositing a tunnel insulation layer, charge trap layer, and charge blocking layer on the exposed sidewalls of the channels, allowing for the formation of single crystal silicon channels and improving layer quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional vertical channel type nonvolatile memory devices are fabricated with tunnel insulation layer and channel formed in sequence, then integration density can be improved, but layer quality of tunnel insulation layer degrades
Solution Approach 1:
The patent applies preliminary action by forming the tunnel insulation layer on the sidewalls of channels before filling the channel openings with conductive material. This sequence ensures that the tunnel insulation layer is formed on clean, exposed sidewalls rather than being deposited over previously formed structures, thereby maintaining high layer quality while achieving improved integration density through vertical channel architecture.
2Reliability
If single crystal silicon channels are formed in conventional vertical channel devices, then current flow is improved, but formation process becomes challenging
Solution Approach 1:
The patent inverts the conventional formation sequence by first forming channels as openings through the substrate and then filling them with single crystal silicon material. This approach reverses the traditional method of growing channels and subsequently creating openings, making it easier to form high-quality single crystal silicon channels with excellent current flow characteristics while simplifying the overall manufacturing process.
3Productivity
If vertical channel structure is implemented, then integration density increases, but area for word line formation increases
Solution Approach 1:
The patent transitions from planar memory cell arrangement to vertical channel structure, moving the memory cells into the third dimension. This dimensional change allows memory cells to be stacked vertically above each other, significantly increasing integration density while reducing the horizontal area required for word line formation and overall device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density of the nonvolatile memory device by improving the layer quality of the tunnel insulation layer, increasing current flow, and ensuring uniform threshold voltage distribution, while also reducing the area required for word line formation.
Implementation Method 1
sequentially forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels
Implementation Method 2
A charge trap type nonvolatile memory device includes a plurality of memory cells, each of which has a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a control gate electrode being formed over a substrate. The charge trap type nonvolatile memory device stores data by trapping charges in a deep-level trap site within the charge trap layer.
Implementation Method 3
etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing sidewalls of the channels by removing the sacrificial layers exposed by the second openings for removal of the sacrificial layers
Data Source
AI summary
A method for fabricating a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing side walls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.