Vertical Channel Memory Nonuniform Gate Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration density of two-dimensional semiconductor memory devices is limited by the minimum feature size in process technology for forming fine patterns, leading to high fabrication costs and complexity, which three-dimensional semiconductor memory devices aim to address.
Innovation Solution
A method of fabricating semiconductor memory devices involves forming a mold stack with alternating insulation and sacrificial layers, creating vertical channel regions, and enlarging spaces between these layers to form gate electrodes, allowing for increased integration density and reduced costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional semiconductor memory devices are used to increase integration density, then manufacturing precision requirements increase, but fabrication costs and process complexity increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertical structures by stacking multiple insulation layers and sacrificial layers vertically. This dimensional change allows integration density to increase without requiring smaller lateral feature sizes, thereby avoiding the need for more complex fine-patterning processes and expensive equipment.
2Ease of manufacture
If three-dimensional semiconductor memory devices are fabricated with uniform gate electrodes, then manufacturing is simpler, but performance is suboptimal due to varying electrical characteristics across the structure
Solution Approach 1:
The patent implements non-uniform gate electrode thicknesses at different lateral positions. Gate electrodes adjacent to sidewalls have greater thickness than those at central positions. This local variation compensates for differences in electrical characteristics caused by the three-dimensional structure, ensuring uniform performance across the device while maintaining the benefits of vertical integration.
Data Source
AI summary
A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.