Vertical Channel Semiconductor Memory Integration
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Solution Overview
Problem
The challenge in semiconductor memory devices is to achieve higher integration while reducing fabrication costs, as two-dimensional devices are limited by the need for expensive equipment for fine pattern formation, and three-dimensional devices require reliable process technologies for mass production.
Innovation Solution
A semiconductor device with a vertical channel structure and interlayer dielectric layers, where the vertical channel has channel recesses corresponding to gate patterns, and an information storage layer insulates the gate patterns from the channel, allowing for increased integration and reduced fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar memory devices are used, then fabrication process is simpler, but integration is limited due to circuit area constraints
Solution Approach 1:
The patent transitions from two-dimensional planar memory devices to three-dimensional vertical channel structures. The vertical channel extends in the vertical direction through multiple interlayer dielectric layers and gate patterns, enabling integration density improvement by utilizing the third dimension (vertical direction) rather than being constrained to the horizontal plane.
2Productivity
If three-dimensional vertical channel structures are implemented, then integration density is improved, but fabrication cost increases due to complex process technology requirements
Solution Approach 1:
The patent divides the vertical channel structure into multiple segments with alternating interlayer dielectric layers and gate patterns. This segmentation allows for standardized repetitive fabrication processes, reducing overall fabrication complexity and cost while maintaining high integration density.
Solution Approach 2:
The patent forms the vertical channel structure first, then sequentially adds interlayer dielectric layers and gate patterns in a preliminary organized manner. This preliminary structuring simplifies subsequent fabrication steps and reduces process complexity.
3Productivity
If fine pattern formation is pursued for higher integration, then circuit area is reduced, but expensive semiconductor equipment is required
Solution Approach 1:
Instead of achieving higher integration by reducing horizontal circuit area through fine pattern formation, the patent utilizes the vertical dimension with channels extending through multiple layers. This approach achieves high integration without requiring the same level of horizontal pattern fineness, thereby reducing equipment cost requirements.
Data Source
AI summary
In semiconductor devices and methods of manufacture, a semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are on the substrate. A plurality of gate patterns are provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material is on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns. The vertical channel has an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns. The vertical channel has an inner sidewall. An information storage layer is present in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.