Vertical Channel Memory Device Erase Operation Simplification
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Solution Overview
Problem
Existing semiconductor memory devices with vertically oriented channels face challenges in controlling the potential of vertical channels, leading to poor reliability and increased complexity due to the need for negative voltage levels and complicated power supply circuits, which are inconsistent with conventional NAND memory devices and result in inefficient erase operations.
Innovation Solution
A semiconductor memory device design where the bottom portion of the vertical channel is directly connected to the substrate at a contact region with a semiconducting material, allowing for the formation of an inversion layer that acts as a common source line, enabling the use of positive erase voltages and simplifying the power circuitry, while maintaining compatibility with conventional NAND devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common source diffusion layer is formed in the substrate with n+ doping to isolate the vertical channel, then the vertical channel is isolated, but it becomes difficult to control the potential of the vertical channel and negative voltage levels are required for erase operations
Solution Approach 1:
The patent removes the n+ common source diffusion layer from the substrate and replaces it with a lightly-doped n-type region. This extraction eliminates the need for negative voltage levels during erase operations, as the vertical channel can be properly controlled through the p-type substrate without requiring complex power supply circuits to generate negative voltages.
Solution Approach 2:
The patent changes the doping parameters of the substrate region beneath the vertical channel from heavily doped n+ to lightly doped n-type. This parameter change allows the vertical channel potential to be controlled through the p-type substrate, eliminating the requirement for negative voltage levels and simplifying the power supply circuitry while maintaining proper channel isolation.
2Reliability
If GIDL operation is used to maintain vertical channel potential, then hole injection is achieved, but hot hole injection into the lower select transistor deteriorates endurance reliability
Solution Approach 1:
The patent converts the harmful GIDL effect, which causes hot hole injection and reliability degradation, into a beneficial structure by using a lightly-doped n-type region instead of a heavily-doped n+ region. This structural change eliminates the GIDL effect while maintaining the ability to control vertical channel potential through the p-type substrate, thereby preventing hot hole injection damage to the lower select transistor.
3Productivity
If vertically oriented channels are used to increase device density, then integration is improved, but the driver transistors must be scaled as a multiple of the number of layers leading to heat removal concerns
Solution Approach 1:
The patent transitions from planar horizontal arrays to vertically oriented channels, moving the device architecture into the third dimension. This dimensional change increases device density by stacking multiple memory layers vertically while maintaining manageable driver transistor sizes, as each layer can share common source and bit line structures, thereby reducing the scaling burden on driver transistors and improving heat removal characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability and efficiency of erase operations by eliminating the need for negative voltage levels, simplifying power supply circuits, and ensuring compatibility with conventional NAND memory devices, thereby improving the overall performance and integration of vertically oriented channel memory devices.
Implementation Method 1
an inversion layer is formed in the contact region to cause the contact region to be conductive by applying a suitable voltage to a lower-most gate of the vertical channel
Data Source
AI summary
In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.