Vertical Channel Memory Device Integration Density
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Solution Overview
Problem
Traditional memory devices face challenges in increasing integration density due to complex manufacturing processes and reduced capacitance in dynamic random access memory (DRAM) cells, particularly in 1T1C and 2T structures, which limits their scalability and efficiency.
Innovation Solution
A memory device design featuring a substrate with read and write transistors arranged in a vertical configuration, utilizing oxide semiconductor materials and a unique gate insulation layer structure to reduce electrical connections and enhance integration, allowing for a simpler manufacturing process and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional 1T1C or 2T memory structures are used, then information storage is achieved, but the manufacturing process becomes complicated and integration density cannot be increased
Solution Approach 1:
The patent combines read and write transistors into a shared vertical channel structure where a single channel serves both read and write operations. This merging eliminates the need for separate transistor structures, simplifying the manufacturing process while maintaining information storage functionality. The gate insulation layer and channel form a unified structure that controls both read and write bit lines.
Solution Approach 2:
The patent transitions from planar transistor structures to vertical channel structures that extend perpendicular to the substrate surface. This dimensional change allows the channel to pass through multiple layers (gate insulation layers and electrodes) vertically, enabling simplified manufacturing while achieving the required electrical isolation and connection functions that traditionally required complex planar arrangements.
2Device complexity
If capacitor area is decreased to increase integration, then integration density improves, but capacitance decreases
Solution Approach 1:
The patent extracts the capacitor component entirely from the memory cell structure, eliminating it replaced by a resistive memory element. This removal of the capacitor allows full utilization of the available area for active memory elements, significantly increasing integration density while the resistive memory element provides sufficient charge storage through its resistance characteristics rather than capacitive storage.
Solution Approach 2:
The patent changes the fundamental storage mechanism from capacitive charge storage to resistive state storage. By using a resistive memory element instead of a capacitor, the system achieves equivalent information storage functionality with different physical parameters, enabling higher integration density without sacrificing storage capability.
3Device complexity
If two transistors are stacked on different layers to increase integration, then integration density improves, but the manufacturing process becomes complicated
Solution Approach 1:
The patent merges the read and write transistor channels into a single vertical channel structure that serves both functions. Instead of stacking two separate transistors on different layers, the invention uses one channel controlled by gate insulation layers and electrodes to manage both read and write bit line connections, thereby achieving high integration without multi-layer transistor stacking complexity.
Solution Approach 2:
The vertical channel structure performs multiple functions simultaneously: it serves as the conduction path for both read and write operations, provides electrical isolation between different bit lines through the gate insulation layers, and enables area-efficient packing. This multi-functional design eliminates the need for separate transistor structures for each function.
Data Source
AI summary
A memory device includes a read word line on a substrate, a first channel extending along a plane perpendicular to an upper surface of the substrate, a second channel facing the first channel in parallel, a first gate insulation layer adjacent to the first channel between the first channel and the second channel, a second gate insulation layer adjacent to the second channel between the first channel and the second channel, a gate electrode adjacent to the first gate insulation layer between the first gate insulation layer and the second gate insulation layer, a write word line adjacent to the second gate insulation layer between the first gate insulation layer and the second gate insulation layer, a read bit line electrically connected to the first channel, and a write bit line electrically connected to the second channel.