Vertical Channel 3D Memory With Self-Aligned Epitaxial Pads
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Solution Overview
Problem
Vertical channel structures in 3D NAND flash memory devices face challenges with high resistance in lower regions and difficulties in maintaining reliable electrical connections between bit lines and thin films in upper regions.
Innovation Solution
The implementation of vertical channel structures with self-aligned epitaxial channel pads, where upper and lower channel pads are formed to provide better electrical connections and reduce resistance, enabling improved conductivity and reliability by connecting vertical channel films to these pads, which are doped for higher conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical channel structures are used in 3D NAND flash memory, then storage density is improved, but resistance in lower regions increases
Solution Approach 1:
The vertical channel structure is segmented into multiple regions with different doping concentrations. The lower region has higher doping concentration to reduce resistance, while upper regions maintain lower doping for proper memory cell operation. This segmentation allows each region to be optimized for its specific function.
Solution Approach 2:
Different regions of the vertical channel structure are given different local properties through selective doping. The lower region receives additional dopant concentration to reduce resistance, while other regions maintain their original doping levels. This local quality modification addresses the resistance issue without affecting the overall memory cell functionality.
2Length of moving object
If thin films are used in upper regions for vertical channel structures, then device scaling is improved, but electrical connection reliability to bit lines deteriorates
Solution Approach 1:
A doped contact region is formed in advance at the upper portion of the vertical channel structure before final bit line connection. This preliminary doped region provides a low-resistance pathway that compensates for the thin film dimensions, ensuring reliable electrical connection to bit lines despite the scaled-down thickness.
Solution Approach 2:
The doping concentration parameter is changed locally in the upper region of the vertical channel structure. By increasing dopant concentration in this specific area, the electrical conductivity is enhanced, providing reliable connection to bit lines even when the overall film thickness is reduced for scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the conductivity of vertical channel structures, particularly in lower regions, and improves the reliability of connections to bit lines and other conductors, addressing the issues of high resistance and connection reliability.
Implementation Method 1
The upper channel pad can be formed by selective epitaxy, forming a self-aligned pad of epitaxial silicon or other material, having a thickness greater than the thickness of the vertical channel film in the vertical channel structure.
Data Source
AI summary
A memory device, which can be configured as a 3D NAND flash memory, includes a stack of conductive strips and an opening through the stack exposing sidewalls of conductive strips on first and second sides of the opening. Some of the conductive strips in the stack are configured as word lines. Data storage structures are disposed on the sidewalls of the stack. A vertical channel film is disposed vertically in contact with the data storage structures. The vertical channel film is connected at a proximal end to an upper channel pad over the stack, and at a distal end to a lower channel pad disposed in a lower level of the opening. The upper and lower channel pads may comprise an epitaxial semiconductor and be thicker than the vertical channel film disposed on the sidewalls of the stack.