Vertical-Channel Memory with Symmetrical Wordline Geometry
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Solution Overview
Problem
As design rules for semiconductor devices decrease, there is a need for new technologies to improve integration density and maintain production yield while enhancing resistance and current driving characteristics, particularly in semiconductor devices with vertical channel transistors.
Innovation Solution
A semiconductor memory device is designed with vertical channel transistors featuring symmetrical channel patterns and wordlines, including horizontal and vertical portions, and a gate insulating pattern between the channel patterns and wordlines, to enhance integration density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design rules are decreased to increase integration density, then integration density improves, but manufacturing precision and production yield worsen
Solution Approach 1:
The patent employs asymmetrical offsetting of wordlines relative to channel patterns to create symmetrical stress distribution. The first wordline is offset in a first direction while the second wordline is offset in a second direction opposite to the first direction, creating a balanced stress field that maintains manufacturing precision despite reduced design rules
Solution Approach 2:
The patent changes the geometric parameters of wordlines by introducing offset distances (first offset distance and second offset distance) that are equal in magnitude but opposite in direction. This parameter adjustment creates symmetrical stress distribution that improves manufacturing precision while maintaining the reduced design rule benefits
2Quantity of substance
If vertical channel transistors are used to increase integration density, then integration density improves, but device complexity increases
Solution Approach 1:
The patent segments the wordline structure into multiple independently controllable wordlines (first wordline and second wordline) with different offset configurations. This segmentation allows independent optimization of each wordline's stress application while maintaining overall device functionality, reducing the complexity burden of vertical channel transistors
3Manufacturing precision
If symmetrical wordline offsetting is implemented to maintain manufacturing precision, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The symmetrical offset configuration serves multiple functions simultaneously: it maintains manufacturing precision by creating balanced stress distribution, enables independent wordline control for enhanced functionality, and provides design flexibility for optimization. This multi-functionality justifies the increased device complexity
Data Source
AI summary
A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.