Vertical Channel MOS Transistor Structure for Chip Miniaturization
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Solution Overview
Problem
Conventional planar type MOS transistors face limitations in further miniaturization, necessitating the development of novel three-dimensional or non-planar transistors to achieve smaller chip sizes and improved performance in semiconductor devices.
Innovation Solution
A semiconductor device with a vertical channel structure is formed by sequentially depositing dielectric layers and creating a channel structure that directly contacts source and drain structures, with a gate structure comprising a conductive layer and gate dielectric layer positioned on the sidewalls and bottom surface of the channel, achieved through specific deposition and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional planar type MOS transistors are used, then the manufacturing process is simple, but further miniaturization is limited
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor architecture to a vertical channel (3D) structure. The channel extends vertically through multiple dielectric layers, with source and drain regions positioned at different heights, enabling miniaturization in the lateral plane while maintaining functional performance through the vertical dimension.
Solution Approach 2:
The transistor structure is divided into distinct vertical segments: source structure in the first dielectric layer, channel structure extending through the second dielectric layer, and drain structure in the third dielectric layer. This segmentation allows independent optimization of each region and simplifies the manufacturing process by enabling sequential formation of components.
2Quantity of substance
If vertical channel structure is implemented, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
Dielectric layers are formed and patterned in advance to create pre-aligned structures before forming the channel and gate. The first, second, and third dielectric layers are sequentially deposited and patterned with predetermined thicknesses and positions, establishing a robust framework that guides subsequent manufacturing steps and maintains alignment precision.
Solution Approach 2:
The second dielectric layer serves as an intermediary medium that facilitates the vertical connection between source and drain structures while providing electrical isolation. The channel structure extends through this dielectric layer, and the gate structure is positioned along its sidewalls, with the dielectric layer enabling precise positioning and alignment of all components.
3Reliability
If gate structure is positioned on sidewalls and bottom surface, then control over channel is improved, but process complexity increases
Solution Approach 1:
The gate structure is positioned in three dimensions along the sidewalls and bottom surface of the vertical channel, creating a wraparound configuration. This 3D gate arrangement provides superior electrostatic control over the channel compared to planar gates, enabling better threshold voltage control and reduced short-channel effects.
Solution Approach 2:
The gate structure serves multiple functions simultaneously: it controls the channel current flow, provides electrical isolation from the channel, and defines the active channel region. The gate dielectric layer positioned between the conductive gate and channel structure enables these multiple functions while simplifying the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables miniaturization, increasing device density and reducing chip size, while simplifying the manufacturing process and reducing costs by allowing for a higher process window and improved manufacturability.
Implementation Method 1
a gate dielectric layer extending along the sidewalls and bottom surface of the conductive layer to physically separate the conductive layer from the channel structure and the second dielectric layer
Implementation Method 2
a channel structure extending through the second dielectric layer and directly contacting the source structure and the drain structure
Data Source
AI summary
A semiconductor device includes a substrate. A first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially disposed on the substrate. A source structure is formed in the first dielectric layer. A drain structure is formed in the third dielectric layer. A channel structure extends through the second dielectric layer and directly contacts the source structure and the drain structure. A gate structure is disposed at two sides of the channel structure. The gate structure includes a conductive layer and a gate dielectric layer. The gate dielectric layer is along sidewalls and a bottom surface of the conductive layer, and is interposed between the conductive layer and the channel structure and the second dielectric layer.