Vertical Channel Gate-All-Around MOSFET Epitaxy CMOS Compatibility
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Solution Overview
Problem
Current manufacturing processes for gate-all-around MOSFETs with vertical channels are not compatible with traditional CMOS processes, leading to increased production costs and complexity, and limitations in further reducing device size due to reliance on high-precision lithography techniques.
Innovation Solution
A method involving epitaxy processes to grow two epitaxial layers with different materials, allowing for the fabrication of vertical channel gate-all-around MOSFETs using conventional CMOS-compatible equipment, which includes steps such as forming source/drain patterns, vertical channel structures, and gate dielectric layers without requiring advanced lithography techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate-all-around MOSFET fabrication processes are used, then device structure can be achieved, but production cost and process complexity increase due to incompatibility with traditional CMOS processes
Solution Approach 1:
The patent changes the material parameter of the channel from traditional silicon to group IV semiconductor materials (Ge, GeSi, SiGe) grown by epitaxy, enabling CMOS-compatible fabrication while achieving the desired gate-all-around device structure with vertical channels
Solution Approach 2:
The patent replaces the mechanical lithography process with an epitaxial growth process to define the channel region. Instead of using photolithography to pattern the channel, the channel structure is formed by selective epitaxial growth of semiconductor materials, eliminating the need for high-precision lithography and reducing process complexity
2Manufacturing precision
If high-precision lithography techniques are used to define gate electrode critical dimension, then device structure can be achieved, but device size reduction is limited
Solution Approach 1:
The patent replaces lithography with epitaxial growth to define the channel critical dimension. The channel width is controlled by the epitaxial growth process parameters (temperature, pressure, gas flow, precursor ratios) rather than by optical lithography resolution, enabling smaller device dimensions without being constrained by lithography wavelength limits
Solution Approach 2:
The patent changes the controlling parameter for critical dimension from lithographic wavelength to epitaxial growth conditions. By adjusting epitaxy parameters such as growth temperature, pressure, and precursor gas ratios, the channel critical dimension can be precisely controlled at dimensions smaller than what is achievable with conventional lithography
3Reliability
If suspended conductive channels are formed on substrate surface, then gate-all-around structure can be achieved, but fabrication process becomes difficult and costly
Solution Approach 1:
Instead of forming suspended channels first and then building the gate around them, the patent inverts the sequence by forming the gate structure first and then growing the channel material around the gate. This is achieved by depositing gate electrode and dielectric layers, then performing selective epitaxial growth to form channels that surround the gate, simplifying the fabrication process
Solution Approach 2:
The selective epitaxial growth process automatically forms the channel structure where needed based on the prepared substrate pattern and masking layers. The growth occurs self-limiting to specific regions defined by the underlying layer structure, eliminating the need for complex suspended channel formation processes and enabling direct integration with CMOS fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the cost-effective fabrication of vertical channel gate-all-around MOSFETs compatible with traditional CMOS processes, facilitating the production of smaller devices and expanding material options for channel materials like Ge, GeSi, and III-V compounds, overcoming size reduction challenges and process complexities.
Implementation Method 1
growing a first epitaxial layer on the top semiconducting layer by an epitaxy process
Data Source
AI summary
A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.