Vertical Channel MRAM Cell Fabrication for Storage Density
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Solution Overview
Problem
Conventional MRAM storage technologies have reached a limit in increasing storage density due to the constraints of reducing the footprint of individual MRAM cells, hindering further advancements in data storage capacity per unit area.
Innovation Solution
The development of vertical channel transistor structures and shared voltage supply contacts within MRAM arrays, combined with advanced fabrication methods such as epitaxial silicon growth and chemical-mechanical planarization, allows for a significant reduction in cell size and increased storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the footprint of individual MRAM cells is decreased to increase storage density, then storage capacity per unit area is improved, but manufacturing complexity and process difficulty increase significantly
Solution Approach 1:
The patent transitions from planar MRAM cell structures to three-dimensional vertical channel structures. The vertical channel extends perpendicular to the substrate, with the magnetoresistive stack positioned at the top, creating a stacked configuration that utilizes the vertical dimension to achieve higher storage density without proportionally increasing manufacturing complexity
Solution Approach 2:
The patent implements a nested structure where the magnetoresistive stack is positioned within and integrated with the vertical channel transistor structure. The tunnel barrier layer, free layer, and reference layer are nested within the vertical channel configuration, allowing multiple functional components to occupy overlapping spatial regions and reducing the overall cell footprint
2Ease of manufacture
If conventional planar MRAM cell structures are used, then manufacturing processes are simpler and more established, but storage density cannot be increased beyond current limits
Solution Approach 1:
The patent segments the MRAM cell into distinct vertical layers and components: the vertical channel transistor structure, the magnetoresistive stack (comprising tunnel barrier, free layer, and reference layer), and interconnecting conductors. This segmentation allows each component to be optimized and fabricated using specialized processes while maintaining overall manufacturability
Solution Approach 2:
The patent employs composite material structures including the magnetoresistive stack combining magnetic layers (free layer, reference layer) with non-magnetic spacer layers and oxide tunnel barriers. These composite structures enable simultaneous achievement of desired magnetic properties, electrical insulation, and compact integration within the vertical channel architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher data storage densities than previously achievable, providing a compact configuration for MRAM while maintaining efficient performance, thereby overcoming the limitations of conventional MRAM storage technologies.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of a cell changes due to the orientation of the magnetic fields of the two layers.
Implementation Method 2
inducing epitaxial silicon structure growth in the at least two holes extending vertically from the doped silicon layer
Implementation Method 3
exposing the planarized nitride layer by performing a chemical-mechanical planarization process
Implementation Method 4
two ferromagnetic plates, or electrodes, that can hold a magnetic field
Implementation Method 5
one of the plates is referred to as the reference layer and has a magnetization which is pinned
Data Source
AI summary
A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.