Vertical Channel MRAM Cells with Epitaxial Growth

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional MRAM storage technologies have reached a limit in increasing storage density due to the constraints of reducing the footprint of individual MRAM cells, hindering further advancements in data storage capacity per unit area.

Innovation Solution

The implementation of a transistor structure with an epitaxially grown vertical channel, a word line surrounding the middle portion of the channel, and a perpendicular magnetic tunnel junction (p-MTJ) sensor coupled to the channel, along with a shared source line configuration, allows for a more compact and efficient memory array design, enabling higher storage densities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the footprint of individual MRAM cells is decreased to increase storage density, then storage capacity per unit area is improved, but the minimum achievable cell size is limited by conventional manufacturing constraints

Engineering Contradiction:
Improvestorage densityVSAvoidcell footprint
Core Design Contradiction:
Quantity of substanceVSLength of moving object

Solution Approach 1:

The patent transitions from planar (2D) MRAM cell architecture to a vertical (3D) architecture by growing epitaxial semiconductor channels vertically from silicon nanowires. This dimensional change allows the channel to extend in the vertical direction rather than requiring proportional increases in lateral footprint, thereby increasing storage density without being constrained by conventional lateral scaling limits.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where the epitaxial semiconductor channel is grown around and integrated with the silicon nanowire core. The vertical channel is positioned within or around the nanowire structure, creating a compact nested arrangement that maximizes space utilization and reduces the overall cell footprint while maintaining functional integrity.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If conventional planar transistor structures are used, then manufacturing is straightforward, but storage density cannot be increased beyond current limits

Engineering Contradiction:
Improvestorage densityVSAvoidtransistor structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent employs vertical epitaxial growth to create three-dimensional transistor structures with channels extending vertically through multiple layers. This vertical architecture integrates the channel, gate, and contact structures in the vertical dimension, achieving higher storage density while managing complexity through systematic layer-by-layer fabrication processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The silicon nanowire serves multiple functions: it acts as the core structural element, provides a template for epitaxial channel growth, and enables vertical integration of multiple device components. This multi-functional role reduces the number of separate manufacturing steps and materials required, managing device complexity while achieving the vertical architecture needed for higher density.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly increases data storage density by reducing the effective cell size and allowing for a larger number of transistors in a given area, overcoming the limitations of conventional MRAM storage technologies.

Implementation Method 1

Due to the spin-polarized electron tunneling effect, the electrical resistance of a cell changes due to the orientation of the magnetic fields of the two layers.

Methodology Applied
Scientific EffectSpin-polarized electron tunneling:

Implementation Method 2

an epitaxially grown vertical channel

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS11222970B2Perpendicular magnetic tunnel junction memory cells having vertical channels
Publication Date: 2022.01.11 INTEGRATED SILICON SOLUTION CAYMAN INC
  • US11222970B2 patent drawing
  • US11222970B2 patent drawing
  • US11222970B2 patent drawing

AI summary

A transistor structure, according to one embodiment, includes: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel. The second side of the vertical channel is opposite the first side of the vertical channel along a plane perpendicular to a deposition direction. A magnetic device, according to another embodiment, includes: a plurality of transistor structures, each of the transistor structures comprising: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel.