3D Vertical Channel NAND Memory Structure with Isolated Bit Lines
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing density while maintaining efficiency, particularly in transitioning from 2-D to 3-D structures and reducing element sizes, which affects memory storage capacity and operational performance.
Innovation Solution
A memory structure comprising a substrate with stacks of alternating conductive and insulating strips, conformally deposited memory and channel layers, dielectric layers, and isolated conductive lines, allowing for a 3-D vertical channel NAND memory configuration with enhanced bit line density and reduced string select line resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3-D structure is used instead of a conventional 2-D structure, then memory density is improved, but device complexity increases
Solution Approach 1:
The patent transitions from a conventional 2-D memory structure to a 3-D vertical channel structure. The memory cells are arranged in vertical stacks extending from the substrate, with channel layers forming vertical channels that penetrate through multiple memory layers. This dimensional change allows significantly higher memory density by utilizing the vertical space above the substrate rather than only the planar area.
Solution Approach 2:
The 3-D memory structure is segmented into multiple functional layers: substrate, alternating conductive and insulating strips forming stacks, memory layers, channel layers, dielectric layers, and conductive lines. Each layer performs a specific function, and this segmentation allows for modular manufacturing and independent optimization of each component while achieving high overall density.
2Quantity of substance
If element sizes are decreased, then memory density is improved, but manufacturing precision requirements increase
Solution Approach 1:
Instead of decreasing element sizes in the planar direction, the patent increases density by extending the structure vertically into the third dimension. The vertical channel layers and memory layers allow for compact packing without requiring extremely small feature sizes in the lateral direction, thereby reducing manufacturing precision requirements.
Solution Approach 2:
The structure employs nested layers where channel layers are conformally disposed on memory layers, which are in turn disposed on stacks. This nested arrangement allows multiple functional elements to be packed within a compact vertical space without requiring excessive lateral miniaturization, thus maintaining manufacturability.
3Quantity of substance
If bit line density is increased, then memory capacity is improved, but string select line resistance increases
Solution Approach 1:
The patent employs alternating conductive and insulating strips forming stacks with different local properties. The conductive strips serve as string select lines with optimized local conductivity, while insulating strips provide isolation. This local differentiation allows high bit line density through vertical stacking while maintaining low resistance in the conductive paths through material selection and geometric optimization.
Solution Approach 2:
The structure uses composite arrangements of conductive and insulating materials in alternating strips. The conductive strips are formulated with materials and dimensions optimized for low resistance, while insulating strips provide electrical isolation. This composite structure enables simultaneous achievement of high density and low resistance by leveraging the complementary properties of different materials in specific spatial configurations.
Data Source
AI summary
A memory structure includes stacks, memory layers, channel layers, dielectric layers, and first conductive lines. Each stack includes a group of alternating conductive strips and insulating strips. The memory layers are conformally disposed on the stacks. The channel layers are conformally disposed on the memory layers. The dielectric layers are disposed on portions of the channel layers at first sides of the stacks and portions of the channel layers at second sides of the stacks. The first conductive lines are disposed along sidewalls of the stacks. The first conductive lines are isolated from the channel layers by the dielectric layers. One first conductive line disposed at the first side of one stack is isolated from one first conductive line disposed at the second side of the same stack and isolated from one first conductive line disposed at the second side of an adjacent stack.